Automating the Layout of Reconfigurable Subsystems via Template Reduction

  • Shawn Phillips
  • Akshay Sharma
  • Scott Hauck
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)


When designing SoCs, a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be used. The inclusion of such devices provides an efficient compromise between the flexibility of software and the performance of hardware, while at the same time allowing for post-fabrication modification of circuits. To automate the layout of reconfigurable subsystems for systems-on-a-chip, we present template reduction. Template reduction enables a designer to eliminate resources from a template that are unnecessary to support the specified application domain. To facilitate this, we have created a feature rich template, from which we automatically generate application specific reconfigurable circuits. Compared to the full template, we achieve designs that are 53.4% smaller and 13.9% faster, while continuing to support the algorithms in a particular application domain.


Functional Unit Application Domain Full Custom Template Architecture VLSI Layout 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Phillips, S.: Automatic Layout of Domain-Specific Reconfigurable Subsystems for Systemon- a-Chip, M.S. Thesis, Northwestern University, Dept. of ECE (July 2001)Google Scholar
  2. 2.
    Sharma, A.: Development of a Place and Route Tool for the RaPiD Architecture, M.S. Thesis, University of Washington (2001)Google Scholar
  3. 3.
    Compton, K., Hauck, S.: Totem: Custom Reconfigurable Array Generation. In: IEEE Symposium on FPGAs for Custom Computing Machines Conference (2001)Google Scholar
  4. 4.
    Compton, K., Sharma, A., Phillips, S., Hauck, S.: Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 59–68. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  5. 5.
    Ebeling, C., Cronquist, D.C., Franklin, P.: RaPiD – Reconfigurable Pipelined Datapath. In: Glesner, M., Hartenstein, R.W. (eds.) FPL 1996. LNCS, vol. 1142, Springer, Heidelberg (1996)Google Scholar
  6. 6.
    Application Specific Programmable Platform using eASICore® Whitepaper Version 1.0 (March 2004),
  7. 7.
    McMurchie, L.E., Ebeling, C.: PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs. In: Symposium on Field-Programmable Gate Arrays, pp.111–117 (1995)Google Scholar
  8. 8.
    Cadence Design Systems, Inc., “Openbook”, version 4.1, release IC 4.4.5 (1999)Google Scholar
  9. 9.
    Cronquist, D.C., Franklin, P., Berg, S.G., Ebeling, C.: Specifying and Compiling Applications for RaPiD. In: IEEE Symposium on FPGAs for Custom Computing Machines (1998)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Shawn Phillips
    • 1
  • Akshay Sharma
    • 1
  • Scott Hauck
    • 1
  1. 1.Department of Electrical EngineeringUniversity of WashingtonSeattle

Personalised recommendations