Abstract
Pattern recognition algorithms are used in experimental High Energy physics for getting parameters (features) of particles tracks in detectors. It is particularly important to have fast algorithms in trigger system. This paper investigates the suitability of using FPGA coprocessor for speedup of the TRT-LUT algorithm – one of the feature extraction algorithms for second level trigger for ATLAS experiment (CERN). Two realization of the same algorithm have been compared: C++ realization tested on a computer equipped with dual Xeon 2.4 GHz CPU, 64-bit, 66 MHz PCI bus, 1024 Mb DDR RAM main memories with Red Hat Linux 7.1 and hybrid C++ – VHDL realisation tested on same PC equipped in addition by MPRACE board (FPGA-Coprocessor board based on Xilinx Virtex-II FPGA and made as 64-bit, 66 MHz PCI card developed at the University of Mannheim). Usage of the FPGA coprocessor can give some reasonable speedup in contrast to general purpose processor only for those algorithms (or parts of algorithms), for which there is a possibility to fulfil calculations with a major degree of parallelism. In case of TRT-LUT algorithm it is the most time consuming parts and using of FPGA coprocessor can give us speed-up by factor more then two for hybrid FPGA/CPU realisation in comparison with CPU only implementation.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
ATLAS Collaboration: ATLAS technical proposal. CERN/LHCC 94-13, CERN, Geneva (1994)
ATLAS Collaboration: ATLAS detector and physics performance TDR. CERN/LHCC 99-14, CERN, Geneva (1999)
Kugel, A.: MPRACE, preliminary documentation. CERN intranet, CERN (2002), http://akugel.home.cern.ch/akugel/mpRace/
ATLAS Inner Detector Community: ATLAS Inner Detector Technical Design Report. CERN/LHCC 97-16, CERN, Geneva (1997)
Clarke, P., Falciano, S., Le, D.P., Lane, J., Abolins, M., Schwick, C., Wickens, F.: Detector and readout specifications, and buffer-RoI relations, for the level-2 studies. ATL-DAQ-99-014, CERN (1999)
Hinkelbein, C., Kugel, A., Männer, R., Müller, M., Sessler, M., Singpiel, H., Baines, J., Bock, R., Smizanska, M.: Pattern recognition in the TRT for the ATLAS B-Physics trigger. ATL-DAQ-99-012, CERN (1999)
Illingworth, J., Kittler, J.: A survey of the Hough transform. Comput. Vision Graphics, Image Processing 44, 87–116 (1988)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Hinkelbein, C., Khomich, A., Kugel, A., Männer, R., Müller, M. (2004). Using of FPGA Coprocessor for Improving the Execution Speed of the Pattern Recognition Algorithm for ATLAS – High Energy Physics Experiment. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_80
Download citation
DOI: https://doi.org/10.1007/978-3-540-30117-2_80
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22989-6
Online ISBN: 978-3-540-30117-2
eBook Packages: Springer Book Archive