Using of FPGA Coprocessor for Improving the Execution Speed of the Pattern Recognition Algorithm for ATLAS – High Energy Physics Experiment
Pattern recognition algorithms are used in experimental High Energy physics for getting parameters (features) of particles tracks in detectors. It is particularly important to have fast algorithms in trigger system. This paper investigates the suitability of using FPGA coprocessor for speedup of the TRT-LUT algorithm – one of the feature extraction algorithms for second level trigger for ATLAS experiment (CERN). Two realization of the same algorithm have been compared: C++ realization tested on a computer equipped with dual Xeon 2.4 GHz CPU, 64-bit, 66 MHz PCI bus, 1024 Mb DDR RAM main memories with Red Hat Linux 7.1 and hybrid C++ – VHDL realisation tested on same PC equipped in addition by MPRACE board (FPGA-Coprocessor board based on Xilinx Virtex-II FPGA and made as 64-bit, 66 MHz PCI card developed at the University of Mannheim). Usage of the FPGA coprocessor can give some reasonable speedup in contrast to general purpose processor only for those algorithms (or parts of algorithms), for which there is a possibility to fulfil calculations with a major degree of parallelism. In case of TRT-LUT algorithm it is the most time consuming parts and using of FPGA coprocessor can give us speed-up by factor more then two for hybrid FPGA/CPU realisation in comparison with CPU only implementation.
KeywordsExecution Speed FPGA Implementation Pattern Recognition Algorithm Feature Extraction Algorithm General Purpose Processor
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