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Power Consumption Reduction Through Dynamic Reconfiguration

  • Michael G. Lorenz
  • Luis Mengibar
  • Mario G. Valderas
  • Luis Entrena
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)

Abstract

Dynamic reconfiguration optimizes the use of hardware resources, and therefore may produce important reductions in power consumption. However, in a reconfigurable system the power consumption produced by the reconfiguration process itself must be taken into account. In this work the reconfiguration power consumption is characterized for a SRAM FPGA. In particular, we show that reconfiguration must be made at the highest frequency available in order to reduce power consumption. The results obtained allow to quantify the tradeoff between the energy saved by the use of dynamic reconfiguration and the energy wasted by the reconfiguration process. In this way, the power consumption reduction that can be obtained with the use of dynamic reconfiguration can be estimated.

Keywords

Power Consumption Power Consumption Reduction Dynamic Reconfiguration Partial Reconfiguration Dynamic Power Consumption 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Michael G. Lorenz
    • 1
  • Luis Mengibar
    • 1
  • Mario G. Valderas
    • 1
  • Luis Entrena
    • 1
  1. 1.Electronic Technology DepartmentMicroelectronics Group Carlos III University of MadridLeganés (Madrid)Spain

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