Abstract
In order to enable efficient integration of FPGAs into cost effective and reliable high-performance systems as well potentially into low power mobile systems, their power efficiency needs to be improved. In this paper, we propose a power management scheme for FPGAs centered on a power-driven partitioning technique. Our power-driven partitioner creates clusters within a design such that within individual clusters, power consumption can be improved via voltage scaling. We tested the effectiveness of our approach on a set of LUT-level benchmark netlists. Further we did constrained placement of the clusters into predefined V\(_{\mbox{\tiny dd}}^{\mbox{\tiny \,\,\,\,\,\,high}}\) and V\(_{\mbox{\tiny dd}}^{\mbox{\tiny \,\,\,\,\,\,low}}\) regions for a single FPGA. Average savings in power consumption with our approach is 48% whereas penalty in channel width and wire length due to constrained placement is 23% and 26% respectively.
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Mukherjee, R., Memik, S.O. (2004). Power-Driven Design Partitioning. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_75
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DOI: https://doi.org/10.1007/978-3-540-30117-2_75
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22989-6
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