A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms

  • Jingzhao Ou
  • Viktor K. Prasanna
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)


A recent trend towards integrating FPGAs with many heterogeneous components, such as memory systems, dedicated multipliers, etc., has made them an attractive option for implementing many embedded systems. Paradoxically, the integration that makes modern FPGAs an attractive computing substrate also makes the development of energy efficient FPGA designs very challenging in practice. This is due to the many alternatives available for implementing a desired functionality and a lack of high-level models of FPGA architectures that can accurately capture the energy dissipation behavior of alternatives. To address these issues, we propose a methodology for energy efficient FPGA designs using malleable algorithms. Malleable algorithms are used to expose the architecture-platform aware specifications of alternate implementations of the desired functionalities. Our methodology consists of three major design steps: domain-specific energy performance modeling, development of malleable algorithms, and system-level optimization. Energy efficient designs are realized through close interaction among these three design steps. To illustrate the proposed design methodology and demonstrate the benefits of designing using malleable algorithms, we present the development of a beamforming application through a high-level MATLAB/Simulink based FPGA design tool developed by us. By tuning the design knobs exposed by malleable algorithms, the design of the beamforming application identified through system-level optimization achieves up to 30% energy reduction compared with other designs considered in our experiments.


Energy Performance FPGA Implementation Register Transfer Level Minimum Variance Distortionless Response FPGA Design 
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  1. 1.
    Altera, Inc.,
  2. 2.
    Choi, S., Scrofano, R., Prasanna, V.K., Jang, J.-W.: Energy Efficient Signal Processing Using FPGAs. In: ACM Int. Symp. on Field-Programmable Gate Arrays, FPGA (2003)Google Scholar
  3. 3.
    Choi, S., Jang, J.-W., Mohanty, S., Prasanna, V.K.: Domain-Specific Modeling for Rapid System-Wide Energy Estimation of Reconfigurable Architectures. In: Engineering of Reconfigurable Systems and Algorithms, ERSA (2002)Google Scholar
  4. 4.
  5. 5.
    Ou, J., Prasanna, V.K.: PyGen: AMATLAB/Simulink based Tool for Synthesizing Parameterized and Energy Efficient Designs Using FPGAs. In: Field-Programmable Custom Computing Machines, FCCM (2004)Google Scholar
  6. 6.
    Ou, J., Choi, S., Prasanna, V.K.: Energy-Efficient Hardware/Software Co-Synthesis for a Class of Applications on Reconfigurable SoCs. Int. Journal of Embedded Systems (2004)Google Scholar
  7. 7.
    Haykin, S.: Adaptive Filter Theory, 3rd edn. Prentice Hall, Englewood Cliffs (1991)zbMATHGoogle Scholar
  8. 8.
    Keutzer, K., Malik, S., Newton, A.R., Rabaey, J.M., Sangiovanni-Vincentelli, A.: System Level Design: Orthogonalization of Concerns and Platform-Based Design. IEEE Trans. on CAD 19(12) (December 2000)Google Scholar
  9. 9.
    Mentor Graphics, Inc.,
  10. 10.
  11. 11.
    Carte Programming Environment, online available at
  12. 12.
    Xilinx, Inc.,

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Jingzhao Ou
    • 1
  • Viktor K. Prasanna
    • 1
  1. 1.Department of Electrical EngineeringUniversity of Southern CaliforniaLos AngelesUSA

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