The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays

  • Steven J. E. Wilton
  • Su-Shin Ang
  • Wayne Luk
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)


This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13μm CMOS high density/high speed FPGA (Altera Stratix EP1S40), and a 0.18μm CMOS low-cost FPGA (Xilinx XC2S200). The results are obtained by both measurements and execution of vendor-supplied tools for power estimation. It is found that pipelining can reduce the amount of energy per operation by between 40% and 90%. Further reduction in energy consumption can be achieved by power-aware clustering, although the effect becomes less pronounced for circuits with a large number of pipeline stages.


Switching Activity Logic Element Pipeline Stage Logic Block Benchmark Circuit 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Steven J. E. Wilton
    • 1
  • Su-Shin Ang
    • 2
  • Wayne Luk
    • 2
  1. 1.Dept. of Electrical and Computer EngUniversity of British ColumbiaVancouverCanada
  2. 2.Department of ComputingImperial College LondonEngland

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