The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays

  • Steven J. E. Wilton
  • Su-Shin Ang
  • Wayne Luk
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)

Abstract

This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13μm CMOS high density/high speed FPGA (Altera Stratix EP1S40), and a 0.18μm CMOS low-cost FPGA (Xilinx XC2S200). The results are obtained by both measurements and execution of vendor-supplied tools for power estimation. It is found that pipelining can reduce the amount of energy per operation by between 40% and 90%. Further reduction in energy consumption can be achieved by power-aware clustering, although the effect becomes less pronounced for circuits with a large number of pipeline stages.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Benini, L., et al.: Glitch power minimization by selective gate freezing. IEEE Trans. VLSI Systems 8(3), 287–298 (2000)CrossRefGoogle Scholar
  2. 2.
    Boemo, E.I., et al.: Some notes on power management on FPGA based systems. In: Moore, W., Luk, W. (eds.) FPL 1995. LNCS, vol. 975, pp. 149–157. Springer, Heidelberg (1995)Google Scholar
  3. 3.
    Chabini, N., et al.: Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs. In: Proc. ACM Great Lakes Symposium on VLSI (2003)Google Scholar
  4. 4.
    Chung, K.S., Kim, T., Liu, C.L.: A complete model for glitch analysis in logic circuits. Journal of Circuits, Systems, and Computers 11(2), 137–154 (2002)Google Scholar
  5. 5.
    Constantinides, G.A.: Perturbation analysis for word-length optimization. In: Proc. Int. Symp. field-Programmable Custom Computing Machines, pp. 81–90 (2003)Google Scholar
  6. 6.
    Hsu, Y.L., Wang, S.J.: Retiming-based logic synthesis for low power. In: Proc. Int. Symp. Low Power Electronics and Design, pp. 275–278. ACM Press, New York (2002)Google Scholar
  7. 7.
    Kandemir, M., et al.: Influence of compiler optimizations on system power. IEEE Trans. VLSI 9(6), 801–804 (2001)CrossRefGoogle Scholar
  8. 8.
    Kim, D., Choi, K.: Power conscious high level synthesis using loop folding. In: Proc. 34th Design Automation Conference (1997)Google Scholar
  9. 9.
    Kumthekar, B., et al.: Power optimization of FPGA-based designs without rewiring. IEE Proc. 147(3), 167–174 (2002)Google Scholar
  10. 10.
    Lamoureux, J., Wilton, S.: On the interaction between power-aware FPGA CAD algorithms. In: Proc. ICCAD (2003)Google Scholar
  11. 11.
    Luk, W., et al.: Parameterized hardware libraries for configurable system-on-chip technology. Canadian Journal of Elect. and Computer Engineering 26(3/4), 125–129 (2001)Google Scholar
  12. 12.
    Marquardt, A., Betz, V., Rose, J.: Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density. ACM/SIGDA Int. Symp. on Field Programmable Gate Arrays, 37–46 (February 1999)Google Scholar
  13. 13.
    Monteiro, J.C., Devadas, S., Ghosh, A.: Retiming sequential circuits for low power. In: Proc. ICCAD, pp. 398–402 (1993)Google Scholar
  14. 14.
    Monteiro, J.C., Oliveira, A.L.: Finite state machine decomposition for low power. In: Proc. 35th Design Automation Conference (1998)Google Scholar
  15. 15.
    Raghunathan, A., Dey, S., Jia, N.K.: Register transfer level power optimization with emphasis on glitch analysis and reduction. IEEE Trans. CAD 18(8), 114–1131 (1999)Google Scholar
  16. 16.
    Reyneri, L.M., et al.: A hardware/software co-design flow and IP library based on Simulink. In: Proc. 38th Design Automation Conference (2001)Google Scholar
  17. 17.
    Singh, A., et al.: Interconnect pipelining in a throughput-intensive FPGA architecture. In: ACM/SIGDA Int. Symp. on Field-Programmable Gate Arrays, pp. 153–160 (2001)Google Scholar
  18. 18.
    Singh, D., Brown, S.: The case for registered routing switches in Field Programmable Gate Arrays. In: ACM/SIGDA Int. Symp. on Field-Programmable Gate Arrays, pp. 161–169 (2001)Google Scholar
  19. 19.
    Stitt, G., et al.: Using on-chip configurable logic to reduce embedded system software energy. In: Proc. Int. Symp. Field-Programmable Custom Computing Machines, pp. 143–151. IEEE Computer Society Press, Los Alamitos (2002)CrossRefGoogle Scholar
  20. 20.
    Sutter, G., et al.: Logic depth, power, and pipeline granularity: updated results on XC4K and Virtex FPGAs. In: Computacion Reconfigurable & FPGAs, Publicaciones Digitales S.A, pp. 201–207 (2003)Google Scholar
  21. 21.
    Tsu, W., et al.: HSRA: High-speed, hierarchical synchronous reconfigurable array. In: ACM Seventh International Symposium on Field-Programmable Gate Arrays (February 1999)Google Scholar
  22. 22.
    Zuchowski, P., et al.: A hybrid ASIC and FPGA architecture. In: Proc. ICCAD, pp. 187–194 (2002)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Steven J. E. Wilton
    • 1
  • Su-Shin Ang
    • 2
  • Wayne Luk
    • 2
  1. 1.Dept. of Electrical and Computer EngUniversity of British ColumbiaVancouverCanada
  2. 2.Department of ComputingImperial College LondonEngland

Personalised recommendations