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Increasing Pipelined IP Core Utilization in Process Networks Using Exploration

  • Claudiu Zissulescu
  • Bart Kienhuis
  • Ed Deprettere
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)

Abstract

At Leiden Embedded Research Center, we are building a tool chain called Compaan/Laura that allows us to do fast mapping of applications written in Matlab onto reconfigurable platforms, such as FPGAs, using IP cores to implement the data-path of the applications. A particular characteristic of the derived networks is the existence of selfloops. These selfloops have a large impact on the utilization of IP cores in the final hardware implementation of a Process Network (PN), especially if the IP cores are deeply pipelined. In this paper, we present an exploration methodology that uses feedback provided by the Laura tool to increase the utilization of IP cores embedded in our PN. Using this exploration, we go from 60MFlops to 1,7GFlops for the QR algorithm using the same number of resources except for memory.

Keywords

Maximum Throughput Read Operation Pipeline Stage Design Space Exploration Tool Chain 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Claudiu Zissulescu
    • 1
  • Bart Kienhuis
    • 1
  • Ed Deprettere
    • 1
  1. 1.Leiden Embedded Research Center, Leiden Institute of Advanced Computer Science (LIACS)Leiden UniversityThe Netherlands

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