Advertisement

Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation

  • T. A. Bartic
  • D. Desmet
  • J-Y. Mignolet
  • T. Marescaux
  • D. Verkest
  • S. Vernalde
  • R. Lauwereins
  • J. Miller
  • F. Robert
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)

Abstract

In order to use Networks-on-Chip as communication infrastructure for heterogeneous, reconfigurable Systems-on-Chip, a set of tools are needed that would allow for an evaluation of the performance of a particular network, and a fast implementation of the system. In this paper we present two models that can be used in the design and implementation of the platform and of its applications. The first model is written in synthesisable VHDL, and it is highly parameterizable allowing a fast network implementation. The second one is a cycle-accurate SystemC model that allows a fast exploration of the design space. The models offer complementary information and help the platform and the application designers to make the best trade-offs. We present how the two models can be used for platform optimization and implementation and for application mapping, using a motion JPEG decoder as a case study. We analyze the system performance as a function of the different design parameters and we present the implementation results for the reconfigurable platform that we have built.

Keywords

Output Buffer Output Queue Crossbar Switch Irregular Topology SystemC Model 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Rowson, J.A., Sangiovanni-Vincentelli, A.: Proc. DAC, pp. 178–183. ACM Press, New York (1997)CrossRefGoogle Scholar
  2. 2.
    Dally, W.J., Towles, B.: Proc. DAC, pp. 684–689. ACM Press, New York (2001)Google Scholar
  3. 3.
    Jantsch, A., Tenhunen, H.: Networks on chip, pp. 3–18. Kluwer Academic, Dordrecht (2003)Google Scholar
  4. 4.
    Benini, L., De Micheli, G.: Comp. 35(1), 70–78 (2002)CrossRefGoogle Scholar
  5. 5.
    Guerrier, P., Greiner, A.: Proc. DATE conf., pp. 250–256. ACM Press, New York (2000)Google Scholar
  6. 6.
    Rijpkema, E., Goossens, K.G.W., Radulescu, A., Dielissen, J., van Meerbergen, J., Wielage, P., Waterlander, E.: Proc. DATE conf. (2003)Google Scholar
  7. 7.
    Kumar, S., Jantsch, A., Soininen, J.-P., Forsell, M., Millberg, M., berg, J., Tiensyrj, K., Hemani, A.: Proc. of IEEE Comp. Soc. Symp. on VLSI (2002)Google Scholar
  8. 8.
    Saastamoinen, I., Siguenza, D., Nurmi, J.: Networks on chip, pp. 193–213. Kluwer Academic, Dordrecht (2003)Google Scholar
  9. 9.
    Nollet, V., Marescaux, T., Verkest, D., Mignolet, J., Vernalde, S.: Proc. DAC (2004)Google Scholar
  10. 10.
  11. 11.
  12. 12.
    Vargas, A.: European Simulation Multiconference (2001)Google Scholar
  13. 13.
    Yi-Ran Sun, S.K., Jantsch, A.: Proc. IEEE Norchip Conf. (2002)Google Scholar
  14. 14.
    Bartic, T., Mignolet, J.-Y., Nollet, V., Marescaux, T., Verkest, D., Vernalde, S., Lauwereins, R.: Proceedings Systems on Chip Conference (2003)Google Scholar
  15. 15.

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • T. A. Bartic
    • 1
  • D. Desmet
    • 1
  • J-Y. Mignolet
    • 1
  • T. Marescaux
    • 1
  • D. Verkest
    • 1
  • S. Vernalde
    • 1
  • R. Lauwereins
    • 1
  • J. Miller
    • 2
  • F. Robert
    • 2
  1. 1.IMECLeuvenBelgium
  2. 2.Université Libre de Bruxelles 

Personalised recommendations