Abstract
In this article we present a compact and efficient co-processor that calculates the Advanced Encryption Standard (AES). It implements the whole functionality of the AES algorithm: all key lengths (128-bit, 192-bit, and 256-bit) are supported for both, encryption and decryption. Furthermore, it supports the Cipher Block Chaining mode. Due to an innovative AES State representation the complete AES co-processor is well suited for low-end FPGAs. The integrated AMBA interface facilitates the integration of the co-processor in System-on-Chip designs too. An implementation on a Xilinx Virtex-E FPGA device uses only 1,125 CLB slices and no block RAMs. Our FPGA implementation reaches a throughput of 215 Mbps at a clock frequency of 161.0 MHz.
The work described in this paper has been supported [in part] by the European Commission through the IST Programme under Contract IST-2002-507932 ECRYPT.
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References
National Institute of Standards and Technology (NIST), Advanced Encryption Standard (AES) Federal Information Processing Standards Publication 197 (FIPS PUB 197) (November 2001)
National Institute of Standards and Technology (NIST), Recommendation for Block Cipher Modes of Operation – Methods and Techniques, NIST Special Publication SP 800-38a (December 2001), http://csrc.nist.gov/publications/nistpubs/
ARM Limited, AMBA 2.0 Specification, http://www.arm.com/armtech/
Chodowiec, P., Khuon, P., Gaj, K.: Fast Implementations of Secret-Key Block Ciphers Using Mixed Inner- and Outer-Round Pipelining. In: Proceedings of the Symposium on Field Programmable Gate Arrays – FPGA 2001, pp. 94–102. ACM Press, New York (2001)
McLoone, M., McCanny, J.: High Performance Single Chip FPGA Rijndael Algorithm Implementations. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 65–76. Springer, Heidelberg (2001)
Fischer, V., Drutarovský, M.: Two Methods of Rijndael Implementation in Reconfigurable Hardware. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 77–92. Springer, Heidelberg (2001)
A. Dandalis, V. Prasanna, J. Rolim, A Comparative Study of Performance of AES Final Candidates Using FGPAs. In: The Third Advanced Encryption Standard (AES) Candidate Conference (2000), Available from http://csrc.nist.gov/CryptoToolkit/aes/round2/conf3/aes3agenda.html
Chodowiec, P., Gaj, K.: Very Compact FPGA Implementation of the AES Algorithm. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 319–333. Springer, Heidelberg (2003)
Mangard, S., Aigner, M., Dominikus, S.: A Highly Regular and Scalable AES Hardware Architecture. IEEE Transactions on Computers 52(4), 483–491 (2003)
Wolkerstorfer, J., Oswald, E., Lamberger, M.: An ASIC implementation of the AES SBoxes. In: Preneel, B. (ed.) CT-RSA 2002. LNCS, vol. 2271, Springer, Heidelberg (2002)
Wolkerstorfer, J.: An ASIC implementation of the AES-MixColumn operation. In: Proceedings of Austrochip 2001, Vienna, Austria, October 12, pp. 129–132 (2001)
Xilinx Incorporated, Silicon Solutions — Virtex Series FPGAs, http://www.xilinx.com/products/
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Pramstaller, N., Wolkerstorfer, J. (2004). A Universal and Efficient AES Co-processor for Field Programmable Logic Arrays. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_58
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DOI: https://doi.org/10.1007/978-3-540-30117-2_58
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