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Automatic Creation of Reconfigurable PALs/PLAs for SoC

  • Mark Holland
  • Scott Hauck
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)

Abstract

Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run-time reconfigurability, or even be used for post-fabrication modifications. Also, by catering the logic to the SoC domain, additional area/delay/power gains can be achieved over current, more general reconfigurable fabrics. This paper presents tools that automate the creation of domain specific PLAs and PALs for SoC, including an Architecture Generator for making optimized arrays and a Layout Generator for creating efficient layouts. By intelligently mapping netlists to PLA and PAL arrays, we can reduce 60%-70% of the programmable connections in the array, creating delay gains of 15%-30% over unoptimized arrays.

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References

  1. 1.
    Compton, K., Hauck, S.: Totem: Custom Reconfigurable Array Generation. In: IEEE Symposium on FPGAs for Custom Computing Machines Conference (2001)Google Scholar
  2. 2.
    Compton, K., Sharma, A., Phillips, S., Hauck, S.: Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems. In: International Symposium on Field Programmable Logic and Applications (2002)Google Scholar
  3. 3.
    Phillips, S., Hauck, S.: Automatic Layout of Domain-Specific Reconfigurable Subsystems for System-on-a-Chip. In: ACM/SIGDA Symposium on Field-Programmable Gate Arrays (2002)Google Scholar
  4. 4.
    Sharma, A.: Development of a Place and Route Tool for the RaPiD Architecture., Master’s Thesis, University of Washington (2001)Google Scholar
  5. 5.
    Yan, A., Wilton, S.: Product Term Embedded Synthesizable Logic Cores. In: IEEE International Conference on Field-Programmable Technology (2003)Google Scholar
  6. 6.
    Mo, F., Brayton, R.K.: River PLAs: A Regular Circuit Structure. In: DAC (2002)Google Scholar
  7. 7.
    Brayton, R.K., Hachtel, G.D., McMullen, C.T., Sangiovanni-Vincentelli, A.L.: Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, Boston (1984)zbMATHGoogle Scholar
  8. 8.
    Betz, V., Rose, J.: VPR: A New Packing, Placement and Routing Tool for FPGA Research. In: International Workshop on Field Programmable Logic and Applications (1997)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Mark Holland
    • 1
  • Scott Hauck
    • 1
  1. 1.Department of Electrical EngineeringUniversity of WashingtonSeattleUSA

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