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Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2

  • Ma José Canet
  • Felip Vicedo
  • Vicenç Almenar
  • Javier Valls
  • Eduardo R. de Lima
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)

Abstract

This paper deals with the design and implementation of a frame, time and frequency synchronizer for Hiperlan/2 WLAN standard. In a packet oriented system, to perform a quick and correct synchronization it is critical to avoid severe bit error rate degradation. So, the design of this subsystem is one of the most challenging tasks to be done in the implementation of a transceiver. In this paper we give practical solutions to the hardware design problems that arise when the synchronization algorithm is turned into a digital circuit. We evaluate the fixed-point realization of the synchronization algorithm and introduce some simplifications to reduce, as much as possible, the cost in area of the circuit without losing its performance.

Keywords

Orthogonal Frequency Division Multiplex Carrier Frequency Offset Detection Failure Orthogonal Frequency Division Multiplex Symbol False Alarm Probability 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Ma José Canet
    • 1
  • Felip Vicedo
    • 2
  • Vicenç Almenar
    • 3
  • Javier Valls
    • 1
  • Eduardo R. de Lima
    • 3
  1. 1.Dpto. Ingeniería ElectrónicaUniversidad Politécnica de ValenciaGandiaSpain
  2. 2.Dpto. Física y Arquitectura ComputadoresUniversidad Miguel HernándezElcheSpain
  3. 3.Dpto. ComunicacionesUniversidad Politécnica de ValenciaGandiaSpain

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