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Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor – An Approach to Tough Cases –

  • Hideharu Amano
  • Takeshi Inuo
  • Hirokazu Kami
  • Taro Fujii
  • Masayasu Suzuki
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)

Abstract

Virtual hardware is difficult to implement even on recent dynamically reconfigurable processors when the loop body of the target application cannot be stored in the set of quickly switch-able contexts. Here, techniques for such tough cases are proposed. Differential configuration which changes only different parts of similar contexts can drastically reduce the time for re-configuration. Pairwise context assignment policy can hide the overhead of configuration with double buffering. Out-of-order context switching enables execution of available context in advance. Through an implementation example on NEC’s DRP-1, it appears that the virtual hardware can be executed with practical speed by combining the proposed techniques.

Keywords

Clock Cycle Physical Context Context Switching Context Group Context Memory 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Ling, X.-P., Amano, H.: WASMII: A Data Driven Computer on a Virtual Hardware. In: Proc. of FCCM, pp. 33–42 (1993)Google Scholar
  2. 2.
    Motomura, M.: A Dynamically Reconfigurable Processor Architecture. Microprocessor Forum (October 2002)Google Scholar
  3. 3.
    Fujii, T., et al.: A Dynamically Reconfigurable Logic Engine with a Multi-Context/ Multi-Mode Unified-Cell Architecture. In: Proc. of Intl. Solid-State Circuits Conf, pp. 360–361 (1999)Google Scholar
  4. 4.
  5. 5.
  6. 6.
  7. 7.
    Caspi, E., et al.: Stream Computations Organized for Reconfigurable Execution (SCORE). In: Grünbacher, H., Hartenstein, R.W. (eds.) FPL 2000. LNCS, vol. 1896, pp. 605–614. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  8. 8.
    Master, P.: The Age of Adaptive Computing Is Here. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 1–3. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  9. 9.
    Smit, G.J.M., Havinga, P.J.M., Smit, L.T., Heysters, P.M.: Dynamic Reconfiguration in Mobile Systems. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 162–170. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  10. 10.
    Horta, E.L., Lockwood, J.W., Partour, D.: Dynamic Hardware Plugins in an FPGA with Partial Run-time Reconfiguration. In: Proc. of DAC 2002 (2002)Google Scholar
  11. 11.
    Trimberger, S., Carberry, D., Johnson, A., Wong, J.: A Time-Multiplexed FPGA. In: Proc. of FCCM, pp. 22–28 (1997)Google Scholar
  12. 12.
    Kaneko, N., Amano, H.: A General Hardware Design Model for Multicontext FPGAs. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 1037–1047. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  13. 13.
    Enzler, R., Plessl, C., Platzner, M.: Virtualzing Hardware with Multi-context Reconfigurable Arrays. In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, pp. 151–160. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  14. 14.
    Lehn, D., et al.: Evaluation of Rapid Context Switching on a CSRC Device. In: Proc. on International Conference on Engineering of Reconfigurable Ssytems and Algorithms (2002)Google Scholar
  15. 15.
    Li, Z., Hauck, S.: Configuration Compression for Virtex FPGA. In: Proc. of FCCM, pp. 143–154 (2001)Google Scholar
  16. 16.
    Kitaoka, T., Amano, H., Anjo, K.: Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device. In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, Springer, Heidelberg (2003)CrossRefGoogle Scholar
  17. 17.
    Yamada, Y., et al.: Core Processor/Multicontext Device Co-design. In: Proc. on Cool Chips VI, p. 82 (2003)Google Scholar
  18. 18.
    Shibata, Y., et al.: A Virtual Hardware System on a Dynamically Reconfigurable Logic Device. In: Proc. of FCCM, pp. 295–296 (2000)Google Scholar
  19. 19.
    Yamamoto, O., et al.: A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems. In: Proc. of FCCM, pp. 291–292 (2000)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Hideharu Amano
    • 1
  • Takeshi Inuo
    • 2
  • Hirokazu Kami
    • 2
  • Taro Fujii
    • 3
  • Masayasu Suzuki
    • 1
  1. 1.Dept. of Information and Computer ScienceKeio University 
  2. 2.NEC Silicons Devices Research LaboratoriesNEC Corporation 
  3. 3.NEC Electronics Corporation 

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