The PowerPC Backend Molen Compiler

  • Elena Moscu Panainte
  • Koen Bertels
  • Stamatis Vassiliadis
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)


In this paper, we report on the backend C compiler developed to target the Virtex II Pro PowerPC processor and to incorporate the Molen architecture programming paradigm. To verify the compiler, we used the multimedia video frame M-JPEG encoder of which the Discrete Cosine Transform (DCT*) function was mapped on the FPGA. We obtained an overall speedup of 2.5 against a maximal theoretical speedup of 2.96. The performance efficiency of 84 % is achieved using automatically generated but non-optimized DCT* hardware implementation.


Discrete Cosine Transform Hardware Implementation VHDL Code Platform FPGA Field Programmable Logic 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Elena Moscu Panainte
    • 1
  • Koen Bertels
    • 1
  • Stamatis Vassiliadis
    • 1
  1. 1.Computer Engineering LabDelft University of TechnologyThe Netherlands

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