Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices
Field-programmable logic devices (FPLDs) are on the verge of revolutionizing the digital signal processing (DSP) industry as programmable DSP microprocessor did nearly two decades ago. Historically, FPLDs were considered to be only a rapid prototyping and low-volume production technology. FPLDs are now attempting to move into the mainstream DSP as their density and performance envelope have steadily improved. While evidence now supports the claim that FPLDs can accelerate selected low-end DSP applications, the technology remains limited in its ability to realize high-end DSP solutions. This is primarily due to systemic weaknesses in FPLD-facilitated arithmetic processing. It will be shown that in such cases, a modified carry save adder (MCSA) arithmetic can become an enabling technology for realizing embedded high-end FPLD-centric DSP solutions. This thesis is developed in the context of a demonstrated MCSA/FPLD synergy and the application of the new technology to communication signal processing. Design synthesis results for Xilinx and Altera FPLDs are provided and show 22-164% speed improvement compared to 2C designs and require lower costs (A*T) in most study cases.
KeywordsDigital Signal Processing Field Programmable Gate Array Residue Number System Speed Improvement Integrator Section
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