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Simultaneous Timing Driven Clustering and Placement for FPGAs

  • Gang Chen
  • Jason Cong
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)

Abstract

Traditional placement algorithms for FPGAs are normally carried out on a fixed clustering solution of a circuit. The impact of clustering on wirelength and delay of the placement solutions is not well quantified. In this paper, we present an algorithm named SCPlace that performs simultaneous clustering and placement to minimize both the total wirelength and longest path delay. We also incorporate a recently proposed path counting-based net weighting scheme [16]. Our algorithm SCPlace consistently outperforms the state-of-the-art FPGA placement flow (T-VPack + VPR) with an average reduction of up to 36% in total wirelength and 31% in longest path delay.

Keywords

Cluster Solution Block Move Placement Algorithm Placement Stage Placement Solution 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Gang Chen
    • 1
  • Jason Cong
    • 1
  1. 1.Computer Science DeparmentUniversity of CaliforniaLos AngelesUSA

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