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A Dual-VDD Low Power FPGA Architecture

  • A. Gayasen
  • K. Lee
  • N. Vijaykrishnan
  • M. Kandemir
  • M. J. Irwin
  • T. Tuan
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)

Abstract

The continuing increase in FPGA size and complexity and the emergence of sub-100nm technology have made FPGA power consumption, both dynamic and static, an important design consideration. In this work, we propose a programmable dual-V DD architecture in which the supply voltage of the logic blocks and routing blocks are programmed to reduce power consumption by assigning low-V DD to non-critical paths in the design, while assigning high-V DD to the timing critical paths in the design to meet timing constraints. We evaluate the effectiveness of different V DD assignment algorithms and architectural implementations. Our experimental results show that reducing the supply voltage selectively to the non-critical paths provides significant power savings with minimal impact on performance. One of our V DD -assignment techniques provides an average power saving of 61% across different MCNC benchmarks.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • A. Gayasen
    • 1
  • K. Lee
    • 1
  • N. Vijaykrishnan
    • 1
  • M. Kandemir
    • 1
  • M. J. Irwin
    • 1
  • T. Tuan
    • 2
  1. 1.Dept. of Computer Science and EngineeringPennsylvania State UniversityUniversity ParkUSA
  2. 2.Xilinx Research LabsSan JoseUSA

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