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Improving FPGA Performance and Area Using an Adaptive Logic Module

  • Mike Hutton
  • Jay Schleicher
  • David Lewis
  • Bruce Pedersen
  • Richard Yuan
  • Sinan Kaptanoglu
  • Gregg Baeckler
  • Boris Ratchev
  • Ketan Padalia
  • Mark Bourgeault
  • Andy Lee
  • Henry Kim
  • Rahul Saini
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)

Abstract

This paper proposes a new adaptable FPGA logic element based on fracturable 6-LUTs, which fundamentally alters the longstanding belief that a 4-LUT is the most efficient area/delay tradeoff. We will describe theory and benchmarking results showing a 15% performance increase with 12% area decrease vs. a standard BLE4. The ALM structure is one of a number of architectural improvements giving Altera’s 90nm Stratix II architecture a 50% performance advantage over its 130nm Stratix predecessor.

Keywords

Logic Module Critical Path Logic Element FPGA Architecture Custom Integrate Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Mike Hutton
    • 1
  • Jay Schleicher
    • 1
  • David Lewis
    • 2
  • Bruce Pedersen
    • 1
  • Richard Yuan
    • 1
  • Sinan Kaptanoglu
    • 1
  • Gregg Baeckler
    • 1
  • Boris Ratchev
    • 1
  • Ketan Padalia
    • 2
  • Mark Bourgeault
    • 2
  • Andy Lee
    • 1
  • Henry Kim
    • 1
  • Rahul Saini
    • 1
  1. 1.Altera San JoseSan JoseUSA
  2. 2.Altera TorontoTorontoCanada

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