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Monte Carlo Radiative Heat Transfer Simulation on a Reconfigurable Computer

  • Maya Gokhale
  • Janette Frigo
  • Christine Ahrens
  • Justin L. Tripp
  • Ron Minnich
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)

Abstract

Recently, the appearance of very large (3 – 10M gate) FPGAs with embedded arithmetic units has opened the door to the possibility of floating point computation on these devices. While previous researchers have described peak performance or kernel matrix operations, there is as yet relatively little experience with mapping an application-specific floating point loop onto FPGAs. In this work, we port a supercomputer application benchmark onto Xilinx Virtex II and Virtex II Pro FPGAs and compare performance with three Pentium IV Xeon microprocessors. Our results show that this application-specific pipeline, with 12 multiply, 10 add/subtract, one divide, and two compare modules of single precision floating point data type, shows speed up of 10.37×. We analyze the trade-offs between hardware and software to characterize the algorithms that will perform well on current and future FPGA architectures.

Keywords

Radiative Heat Transfer Point Library Loop Iteration Single Precision Spatial Parallelism 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Maya Gokhale
    • 1
  • Janette Frigo
    • 1
  • Christine Ahrens
    • 1
  • Justin L. Tripp
    • 1
  • Ron Minnich
    • 1
  1. 1.Los Alamos National Laboratory 

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