Abstract
This paper describes a novel Configurable System-on-Chip (CSoC) architecture for stream-based computations and real-time signal processing. It offers high computational performance and a high degree of flexibility and adaptability by employing a micro Task Controller (mTC) unit in conjunction with programmable and configurable hardware. The hierarchically organized architecture provides a programming model, allows an efficient mapping of applications and is shown to be easy scalable to future VLSI technologies where over a hundred processing cells on a single chip will be feasible to deal with the inherent dynamics of future application domains and system requirements. Several mappings of commonly used digital signal processing algorithms and implementation results are given for a standard-cell ASIC design realization in 0.18 micron 6-layer UMC CMOS technology.
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Wallner, S. (2004). A Configurable System-on-Chip Architecture for Embedded Devices. In: Yew, PC., Xue, J. (eds) Advances in Computer Systems Architecture. ACSAC 2004. Lecture Notes in Computer Science, vol 3189. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30102-8_6
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DOI: https://doi.org/10.1007/978-3-540-30102-8_6
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23003-8
Online ISBN: 978-3-540-30102-8
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