Abstract
As device sizes continue shrinking, lower charges are needed to activate gates, and consequently ever smaller external events (such as single ionizing particles of naturally occurring radiation) will be able to upset the correct functioning of complex modern microprocessors. Therefore, designers of future processors must take this new fact into account and should incorporate in their design fault-tolerant features which will allow processors to continue operating correctly even when such faults have occurred. Many faulty conditions are control flow errors which cause processors to violate the correct sequencing of instructions. Indeed, they amount to between 33% and 77% of all run-time errors. We present here a new compile-time signature assignment algorithm (the signature checking technique is a well-known approach to detect control flow errors). We also present the theoretical proof as well as the fault detection coverage analysis of our algorithm. We then describe the required enhancement to the basic microarchitecture: an on-chip assigned-signature checker which is capable of executing three additional instructions (SIC, SIJ, SIJC). This allows the processor to efficiently check the run-time sequence and detect control flow errors.
This paper is based upon work supported in part by NSF grants CCR-0234444 and INT-0223647. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation.
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References
Hennessy, J.L., Patterson, D.A.: Computer Architecture:A Quantitative Approach, 3rd edn. Morgan Kaufmann Publishers, Inc., San Francisco (2002)
Borkar, S.: Design Challenges of Technology Scaling. IEEE Micro (1999)
Yang, P., Chern, J.H.: Design for Reliability: The Major Challenge for VLSI. Proceedings of the IEEE (1999)
Reinhardt, S.K., Mukherjee, S.S.: Transient Fault Detection via Simultaneous Multithreading. In: 27th International Symposium on Computer Architecture (2000)
Hennessy, J.: The Future of Systems Research. IEEE Computer (1999)
Quach, N.: High Availability and Reliability in the Itanium Processor. IEEE Micro (2000)
Bossen, D.C., Tendler, J.M., Reick, K.: Power4 System Design for High Reliability. IEEE Micro (2002)
Ando, H., Yoshida, Y., Inoue, A., Sugiyama, I., Asakawa, T., Morita, K., Muta, T., Motokurumada, T., Okada, S., Yamashita, H., Satsukawa, Y., Konmoto, A., Yamashita, R., Sugiyama, H.: A 1.3-GHz Fifth-Generation SPARC64 Microprocessor. IEEE Journal of Solid-State Circuits (2003)
Wilken, K., Shen, J.P.: Continuous signature monitoring: Low-Cost Concurrent-Detection of Processor Control Errors. IEEE Transactions on Computer-Aided Design (1990)
Ohlsson, J., Rimen, M., Gunneflo, U.: A Study of the Effects of Transient Fault Injection Into a 32-bit RISC with Built-in Watchdog. In: 29th International Symposium on Fault-Tolerant Computing (1991)
Schuette, M.A., Shen, J.P.: Processor Control Flow Monitoring Using Signatured Instruction Streams. IEEE Transactions on Computers (1987)
Mohmood, A., McCluskey, E.J.: Concurrent Error Detection Using Watchdog Processors – A Survey. IEEE Transactions on Computers (1988)
Schuette, M.A., Shen, J.P.: Exploiting Instruction-Level Parallelism for Integrated Control- Flow Checking. IEEE Transactions on Computers (1994)
Warter, N.J., Hwu, W.M.W.: A Software Based Approach to Achieving Optimal Performance for Signature Control Flow Checking. In: 20th International Symposium on Fault-Tolerant Computing (1990)
Michel, T., Leveugle, R., Saucier, G.: A New Approach to Control Flow Checking without Program Modification. In: 21st International Symposium on Fault-Tolerant Computing (1991)
Alkhalifa, Z., Nair, S., Krishnamurthy, N., Abraham, J.A.: Design and Evaluation of System- Level Checks for On-Line Control Flow Error Detection. IEEE Transactions on Parallel and Distributed Systems (1999)
Shirvani, P.P., McCluskey, E.J.: Fault-Tolerant Systems in a Space Environment: The CRC ARGOS Project. Technical Report CRC-TR 98-2, Stanford University (1998)
Bagchi, S., Srinivasan, B., Whisnant, K., Kalbarczyk, Z., Iyer, R.K.: Hierarchical Error Detection in a Software Implemented FaultTolerance (SIFT) Environment. IEEETransactions on Knowledge and Data Engineering (2000)
Oh, N., Shirvani, P.P., McCluskey, E.J.: Control-Flow Checking by Software Signatures. IEEE Transactions on Reliability (2002)
Aho, A.V., Sethi, R., Ullman, J.D.: Compilers: Principles, Techniques, and Tools. Addison-Wesley Publishing Company, Reading (1986)
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Li, X., Gaudiot, JL. (2004). A Compiler-Assisted On-Chip Assigned-Signature Control Flow Checking. In: Yew, PC., Xue, J. (eds) Advances in Computer Systems Architecture. ACSAC 2004. Lecture Notes in Computer Science, vol 3189. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30102-8_46
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DOI: https://doi.org/10.1007/978-3-540-30102-8_46
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