A Compiler-Assisted On-Chip Assigned-Signature Control Flow Checking

Abstract

As device sizes continue shrinking, lower charges are needed to activate gates, and consequently ever smaller external events (such as single ionizing particles of naturally occurring radiation) will be able to upset the correct functioning of complex modern microprocessors. Therefore, designers of future processors must take this new fact into account and should incorporate in their design fault-tolerant features which will allow processors to continue operating correctly even when such faults have occurred. Many faulty conditions are control flow errors which cause processors to violate the correct sequencing of instructions. Indeed, they amount to between 33% and 77% of all run-time errors. We present here a new compile-time signature assignment algorithm (the signature checking technique is a well-known approach to detect control flow errors). We also present the theoretical proof as well as the fault detection coverage analysis of our algorithm. We then describe the required enhancement to the basic microarchitecture: an on-chip assigned-signature checker which is capable of executing three additional instructions (SIC, SIJ, SIJC). This allows the processor to efficiently check the run-time sequence and detect control flow errors.

This paper is based upon work supported in part by NSF grants CCR-0234444 and INT-0223647. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation.