Initial Experiences with Dreamy Memory and the RAMpage Memory Hierarchy

  • Philip Machanick
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3189)


This paper is a first look at the value of the RAMpage memory hierarchy to low-energy design. The approach used, dreamy memory, is to put DRAM in a low-power mode, unless it is referenced. Simulation results show that RAMpage provides a better overall speed-energy compromise than the conventional architecture used for comparison. The most energy-efficient RAMpage configuration in dreamy mode ran 3% faster and used 71% of the energy for DRAM of the best dreamy run of the conventional model. As compared with the best non-dreamy run time, the best dreamy time was 9% slower, but used under 17% of the energy for DRAM. The lowest-energy dreamy simulation used less than 16% of the DRAM energy of the fastest non-dreamy version, a very useful gain, given that DRAM uses significantly more power than the processor in a low-energy design. The most energy-efficient variant ran 12% slower than the fastest, allowing several trade-offs between speed and energy.


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  1. 1.
    ARM. The ARM11 Microprocessor and ARM PrimeXsys Platform. ARM (October 2002),
  2. 2.
    Benini, L., Macii, A., Poncino, M.: From Energy-aware design of embedded memories: A survey of technologies, architectures, and optimization techniques. From ACM Trans. on Embedded Computing Sys. 2(1), 5–32 (2003)CrossRefGoogle Scholar
  3. 3.
    Binkert, N.L., Hallnor, E.G., Reinhardt, S.K.: From Network-oriented fullsystem simulation using M5. In: From In Sixth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW), February 2003, pp. 36–43 (2003)Google Scholar
  4. 4.
    : From Data memory design considering effective bitwidth for low-energy embedded systems. In: From In Proc. 15th Int. Symp. on System Synthesis, Kyoto, Japan, pp. 201–206 (2002)Google Scholar
  5. 5.
    Uwe Dannowski, Kevin Elphinstone, Jochen Liedtke, Gerd Liefländer, Espen Skoglund, Volkmar Uhlig, Christian, Ceelen Andreas, and Haeberlen Marcus Völp. From The L4Ka vision. From Technical report, University of Karlsruhe, System Architecture Group, April 2001. From Google Scholar
  6. 6.
    Richard Fromm, Stylianos Perissakis, Neal Cardwell, Christoforos Kozyrakis, Bruce McGaughy, David Patterson, Tom Anderson, and Katherine Yelick. From The energy efficiency of IRAM architectures. From In Proc. 24th Int. Symp. on Computer Architecture, pages 327–337, Denver, CO, 1997. Google Scholar
  7. 7.
    J.L. Hennessy and D.A. Patterson. From Computer Architecture: A Quantitative Approach. From Morgan Kauffmann, San Francisco, CA, 3rd edition, 2003. Google Scholar
  8. 8.
    Hai Huang, Padmanabhan Pillai, and Kang G. Shin. From Design and implementation of power-aware virtual memory. From In Proc. USENIX 2003 Annual Technical Conference, pages 57–70, San Antonio, Tx, June 2003. Google Scholar
  9. 9.
    E.E. Johnson. From Graffiti on the memory wall. From Computer Architecture News, 23(4):7–8, September 1995. Google Scholar
  10. 10.
    Stefanos Kaxiras, Zhigang Hu, and Margaret Martonosi. From Cache decay: exploiting generational behavior to reduce cache leakage power. From In Proc. 28th Ann. Int. Symp. on Computer architecture, pages 240–251, G teborg, Sweden, 2001. Google Scholar
  11. 11.
    Alvin R. Lebeck, Xiaobo Fan, Heng Zeng, and Carla Ellis. From Power aware page allocation. From In Proc. 9th Int. Conf. on Arch. Support for Programming Languages and Operating Systems (ASPLOS-9), pages 105–116, Cambridge, MA, November 2000. Google Scholar
  12. 12.
    P. Machanick. From The case for SRAM main memory. From Computer Architecture News, 24(5):23–30, December 1996. Google Scholar
  13. 13.
    P. Machanick. From Correction to RAMpage ASPLOS paper. From Computer Architecture News, 27(4):2–5, September 1999. Google Scholar
  14. 14.
    P. Machanick. From Scalability of the RAMpage memory hierarchy. From South African Computer Journal, (25):68–73, August 2000. Google Scholar
  15. 15.
    P. Machanick and Z. Patel. From L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy. From In Proc. Eighth Asia-Pacific Computer Systems Architecture Conf., pages 305–319, Aizu-Wakamatsu City, Japan, September 2003. Google Scholar
  16. 16.
    P. Machanick, P. Salverda, and L. Pompe. From Hardware-software trade-offs in a Direct Rambus implementation of the RAMpage memory hierarchy. From In Proc. 8th Int. Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), pages 105–114, San Jose, CA, October 1998. Google Scholar
  17. 17.
    Micron Technology. From 256Mb: x4, x8, x16 DDR SDRAM, December 2003. From Data Sheet, Google Scholar
  18. 18.
    NEC. From MOS integrated circuit μPD4482162, 4482182, 4482322, 4482362, December 2002. From Data Sheet No. M14522EJ3V0DS00, Google Scholar
  19. 19.
    Ashley Saulsbury, Fong Pong, and Andreas Nowatzyk. From Missing the memory wall: the case for processor/memory integration. From In Proc. 23rd Ann. Int. Symp. on Computer architecture, pages 90–101, 1996. Google Scholar
  20. 20.
    Hojun Shim, Yongsoo Joo, Yongseok Choi, Hyung Gyu Lee, and Naehyuck Chang. From Low-energy off-chip SDRAM memory systems for embedded applications. From Trans. on Embedded Computing Sys., 2(1):98–130, 2003. Google Scholar
  21. 21.
    W.A. Wulf and S.A. McKee. From Hitting the memory wall: Implications of the obvious. From Computer Architecture News, 23(1):20–24, March 1995.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Philip Machanick
    • 1
  1. 1.School of ITEEUniversity of QueenslandBrisbaneAustralia

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