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Initial Experiences with Dreamy Memory and the RAMpage Memory Hierarchy

  • Philip Machanick
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3189)

Abstract

This paper is a first look at the value of the RAMpage memory hierarchy to low-energy design. The approach used, dreamy memory, is to put DRAM in a low-power mode, unless it is referenced. Simulation results show that RAMpage provides a better overall speed-energy compromise than the conventional architecture used for comparison. The most energy-efficient RAMpage configuration in dreamy mode ran 3% faster and used 71% of the energy for DRAM of the best dreamy run of the conventional model. As compared with the best non-dreamy run time, the best dreamy time was 9% slower, but used under 17% of the energy for DRAM. The lowest-energy dreamy simulation used less than 16% of the DRAM energy of the fastest non-dreamy version, a very useful gain, given that DRAM uses significantly more power than the processor in a low-energy design. The most energy-efficient variant ran 12% slower than the fastest, allowing several trade-offs between speed and energy.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Philip Machanick
    • 1
  1. 1.School of ITEEUniversity of QueenslandBrisbaneAustralia

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