Improving the Security of Dual-Rail Circuits

  • Danil Sokolov
  • Julian Murphy
  • Alex Bystrov
  • Alex Yakovlev
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3156)


Dual-rail encoding, return-to-spacer protocol and hazard-free logic can be used to resist differential power analysis attacks by making the power consumption independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g. all-zeroes, which gives rise to power balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in each clock cycle regardless of the transmitted data values. To generate these dual-rail circuits an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the Advanced Encryption Standard (AES) have been simulated and compared in order to evaluate the method.


Smart Card Clock Cycle Advance Encryption Standard Code Word Switching Activity 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Danil Sokolov
    • 1
  • Julian Murphy
    • 1
  • Alex Bystrov
    • 1
  • Alex Yakovlev
    • 1
  1. 1.School of Electrical, Electronic and Computer EngineeringUniversity of NewcastleNewcastle upon TyneUK

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