Performance Estimation of Streaming Media Applications for Reconfigurable Platforms

  • Carsten Reuter
  • Javier Martín Langerwerf
  • Hans-Joachim Stolberg
  • Peter Pirsch
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3133)


A methodology for performance estimation of streaming media applications for different platforms is presented. The methodology derives a complexity profile for an application as a platform-independent metric, and enables performance estimation on potential platforms by correlating the complexity profile with platform-specific data. By example of an MPEG-4 Advanced Simple Profile (ASP) video decoder, performance estimation results are presented. As one particular benefit, the approach can be employed to explore what hardware functions are most suited for the implementation on reconfigurable architectures.


Performance Estimation Input Stream Video Decoder Core Task Input Data Stream 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Peleg, A., Weiser, U.: MMX Technology Extension to the Intel Architecture. IEEE Micro, 42–50 (1996)Google Scholar
  2. 2.
    Xilinx, Inc.: Virtex-II Pro Platform FPGA (2003)Google Scholar
  3. 3.
    Kuroda, I., Nishitani, T.: Multimedia Processors. Proc. IEEE. 86, 1203–1221 (1998)CrossRefGoogle Scholar
  4. 4.
    Kuhn, P.M., Stechele, W.: Complexity Analysis of the Emerging MPEG-4 Standard as a Basis for VLSI Implementation. In: SPIE Visual Commun. Image Process, San Jose, vol. 3309, pp. 498–509 (1998)Google Scholar
  5. 5.
    ISO/IEC 14496-2:1999/Amd.1:2000: Coding of Audio-Visual Objects - Part 2: Visual, Amendment 1: Visual Extensions (1999)Google Scholar
  6. 6.
    ISO/IEC 14496-2:1999/FDAM4: Amendment 4: Streaming Video Profile (2000)Google Scholar
  7. 7.
    ISO/IEC JTC1/SC29/WG11 N3093: MPEG-4 Video Verification Model Version 15.0 (1999)Google Scholar
  8. 8.
    ISO/IEC JTC1/SC29/WG11 N2918: MoMuSys Implementation of the VM, VM-991029 (1999)Google Scholar
  9. 9.
    Hovden, G., Ling, N.: On Speed Optimization of MPEG-4 Decoder for Real-Time Multimedia Applications. In: Proc. 3rd Int. Conf. Computational Intelligence and Multimedia Applications, New Delhi, pp. 399–402 (1999)Google Scholar
  10. 10.
    Benini, L., de Micheli, G., Macii, E.: Designing Low-Power Circuits: Practical Recipes. IEEE Circuits and Systems Magazine 1, 6–25 (2001)CrossRefGoogle Scholar
  11. 11.
    Lan, T., Chen, Y., Zhong, Z.: MPEG2 Decoding Complexity Regulation for a Media Processor. In: Proc. 2001 Workshop on Multimedia Signal Processing, pp. 193–198 (2001)Google Scholar
  12. 12.
    Stolberg, H.J., Bereković, M., Pirsch, P., Runge, H.: The MPEG-4 Advanced Simple Profile - A Complexity Study. In: Proc. IEEE 2nd Workshop and Exhibition on MPEG-4 (2001)Google Scholar
  13. 13.
    Stolberg, H.J., Bereković, M., Pirsch, P., Runge, H., Möller, H., Kneip, J.: The M-PIRE MPEG-4 CODEC DSP and its Macroblock Engine. In: Proc. IEEE Int. Symp. Circ. Syst (ISCAS), vol. II, pp. 192–195 (2000)Google Scholar
  14. 14.
    Xilinx, Inc.: CORE Generator Guide (2002)Google Scholar
  15. 15.
    Nallatech Limited: BenERA User Guide (2002)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Carsten Reuter
    • 1
  • Javier Martín Langerwerf
    • 1
  • Hans-Joachim Stolberg
    • 1
  • Peter Pirsch
    • 1
  1. 1.Institute of Microelectronic SystemsUniversity of HannoverHannoverGermany

Personalised recommendations