Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting

  • Jianjiang Ceng
  • Weihua Sheng
  • Manuel Hohenauer
  • Rainer Leupers
  • Gerd Ascheid
  • Heinrich Meyr
  • Gunnar Braun
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3133)


Today’s Application Specific Instruction-set Processor (ASIP) design methodology often employs centralized Architecture Description Language (ADL) processor models, from which software tools, such as C compiler, assembler, linker, and instruction-set simulator, can be automatically generated. Among these tools, the C compiler is becoming more and more important. However, the generation of C compilers requires high-level architecture information rather than low-level details needed by simulator generation. This makes it particularly difficult to include different aspects of the target architecture into one single model, and meanwhile keeping consistency.

This paper presents a modeling style, which is able to capture high- and low-level architectural information at the same time and drives both the C compiler and the simulator generation without sacrificing the modeling flexibility. The proposed approach has been successfully applied to model a number of contemporary, real-world processor architectures.


Simulator Generation Modeling Style Architecture Description Language Design Automation Conference Processor Model 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    EXPRESSION User Manual (version 1.0),
  2. 2.
    ACE – Associated Computer Experts bv. The COSY Compiler Development System,
  3. 3.
    Aho, A., Ganapathi, M., Tjiang, S.: Code generation using tree matching and dynamic programming. IEEE Transactions on Programming Languages and Systems 11(4), 491–516 (1989)CrossRefGoogle Scholar
  4. 4.
    Aho, A., Sethi, R., Ullman, J.: Compilers, Principles, Techniques and Tools. Addison-Wesley, Reading (January 1986) ISBN 0-2011-0088-6Google Scholar
  5. 5.
    Bashford, S., Bieker, U., Harking, B., Leupers, R., Marwedel, P., Neumann, A., Voggenauer, D.: The MIMOLA Language, Version 4.1. Reference Manual, Department of Computer Science 12, Embedded System Design and Didactics of Computer Science (1994)Google Scholar
  6. 6.
    Braun, G., Leupers, R., Asheid, G., Meyr, H.: A Novel Approach for Flexible and Consistent ADL-driven ASIP Design. In:Proc. of the Design Automation Conference (DAC) (March 2004)Google Scholar
  7. 7.
    CoWare Inc. LISATek product family,
  8. 8.
    Fauth, J.: Van Praet, and M. Freericks. Describing Instruction Set Processors Using nML. In: Proc. of the European Design and Test Conference (ED & TC) (March 1995)Google Scholar
  9. 9.
    Hadjiyiannis, G., Hanono, S., Devadas, S.: ISDL: An Instruction Set Description Language for Retargetability. In: Proc. of the Design Automation Conference (DAC) (June 1997)Google Scholar
  10. 10.
    Halambi, P., Grun, V., Ganesh, A., Khare, N.: Dutt, and A. Nicolau. EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability. In: Proc. of the Conference on Design, Automation & Test in Europe (DATE) (March 1999)Google Scholar
  11. 11.
    Hanono, S., Devadas, S.: Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator. In: Design Automation Conference, pp. 510–515 (1998)Google Scholar
  12. 12.
    Hoffmann, A., Kogel, T., Nohl, A., Braun, G., Schliebusch, O., Wahlen, O., Wieferink, A., Meyr, H.: A Novel Methodology for the Design of Application Specific Instruction Set Processors (ASIP) Using a Machine Description Language. IEEE Transactions on Computer-Aided Design 20(11), 1338–1354 (2001)CrossRefGoogle Scholar
  13. 13.
    Hoffmann, A., Leupers, R., Meyr, H.: Architecture Exploration for Embedded Processors with LISA. Kluwer Academic Publishers, Boston (January 2003) ISBN 1- 4020-7338-0Google Scholar
  14. 14.
    Hohenauer, M., Scharwaechter, H., Karuri, K., Wahlen, O., Kogel, T., Leupers, R., Ascheid, G., Meyr, H.: A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models.In: Proc. of the Conference on Design, Automation & Test in Europe (DATE) (March 2004)Google Scholar
  15. 15.
    Homewood, F., Faraboschi, P.: ST200: A VLIWArchitecture for Media-Oriented Applications. Microprocessor Forum (October 2000)Google Scholar
  16. 16.
    Leupers, R., Marwedel, P.: A BDD-based frontend for retargetable compilers. In: Proc. of the European Design and Test Conference (ED & TC), pp. 239–243 (1995)Google Scholar
  17. 17.
    Nie, X., Gazsi, L., Engel, F., Fettweis, G.: A new network processor architecture for high-speed communications. In: Proc. of the IEEE Workshop on Signal Processing Systems (SIPS), pp. 548–557 (October 1999)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Jianjiang Ceng
    • 1
  • Weihua Sheng
    • 1
  • Manuel Hohenauer
    • 1
  • Rainer Leupers
    • 1
  • Gerd Ascheid
    • 1
  • Heinrich Meyr
    • 1
  • Gunnar Braun
    • 2
  1. 1.Integrated Signal Processing SystemsAachen University of Technology (RWTH)AachenGermany
  2. 2.CoWare, Inc.AachenGermany

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