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Cycle Accurate Simulation Model Generation for SoC Prototyping

  • Antoine Fraboulet
  • Tanguy Risset
  • Antoine Scherrer
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3133)

Abstract

We present new results concerning the integration of high level designed ips into a complete System on Chip. We first introduce a new computation model that can be used for cycle accurate simulation of register transfer level synthesized hardware. Then we provide simulation of a SoC integrating a data-flow ip synthesized with MMAlpha and the SocLib cycle accurate simulation environment. This integration also validates an efficient generic interface mechanism for data-flow ips.

Keywords

Register Transfer Level Hardware Accelerator Transaction Level Modeling Simple Operating System Code Duplication 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Antoine Fraboulet
    • 1
  • Tanguy Risset
    • 2
  • Antoine Scherrer
    • 2
  1. 1.Citi, Insa-LyonVilleurbanne Cedex
  2. 2.LIP, ENS LyonLyon Cedex 07

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