HIBI v.2 Communication Network for System-on-Chip

  • Erno Salminen
  • Vesa Lahtinen
  • Tero Kangas
  • Jouni Riihimäki
  • Kimmo Kuusilinna
  • Timo D. Hämäläinen
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3133)


This paper presents a communication network targeted for complex system-on-chip (SoC) and network-on-chip (NoC) designs. The Heterogeneous IP Block Interconnection v.2 (HIBI) aims at maximum efficiency and energy saving per transmitted bit combined with guaranteed quality-of-service (QoS) in transfers. Other features include support for arbitrary topologies with several clock domains, flexible scalablility in signalling and run-time reconfiguration of network parameters. HIBI has been implemented in VHDL and SystemC and synthesized in 0.18 CMOS technology with area comparable to other NoC wrappers. HIBI data transfers are shown to approach the maximum theoretical performance for protocol efficiency.


Time Slot Intellectual Property Clock Cycle Intellectual Property Core Clock Domain 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Erno Salminen
    • 1
  • Vesa Lahtinen
    • 1
  • Tero Kangas
    • 1
  • Jouni Riihimäki
    • 1
  • Kimmo Kuusilinna
    • 1
  • Timo D. Hämäläinen
    • 1
  1. 1.Institute of Digital and Computer SystemsTampere University of TechnologyTampereFinland

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