Scalable FFT Processors and Pipelined Butterfly Units

  • Jarmo Takala
  • Konsta Punkka
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3133)


This paper considers partial-column radix-2 FFT processors. The efficiency of processors based on bit-parallel multipliers, distributed arithmetic, and CORDIC is analyzed with the aid of logic synthesis.


Fast Fourier Transform Fast Fourier Transform Algorithm CORDIC Algorithm Clock Constraint Twiddle Factor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Cooley, J., Tukey, J.: An algorithm for the machine calculation of the complex Fourier series. Math. Comput. 19, 297–301 (1965)zbMATHCrossRefMathSciNetGoogle Scholar
  2. 2.
    Tran-Thong, L.B.: Fixed-point fast Fourier transform error analysis. IEEE Trans. Acoust., Speech, Signal Processing 24, 563–573 (1976)CrossRefMathSciNetGoogle Scholar
  3. 3.
    Granata, J., Conner, M., Tolimieri, R.: Recursive fast algorithms and the role of the tensor product. IEEE Trans. Signal Processing 40, 2921–2930 (1992)zbMATHCrossRefGoogle Scholar
  4. 4.
    Gorman, S.F., Wills, J.M.: Partial column FFT pipelines. IEEE Trans. Circuits Syst. II 42, 414–423 (1995)zbMATHCrossRefGoogle Scholar
  5. 5.
    Wold, E.H., Despain, A.M.: Pipeline and parallel-pipeline FFT processors for VLSI implementations. IEEE Trans. Comput. 33, 414–426 (1984)zbMATHCrossRefGoogle Scholar
  6. 6.
    Wosnitza, M., Cavadini, M., Thaler, M., Tröster, G.: A high precision 1024-point FFT processor for 2D convolution. In: Dig. Tech. Papers IEEE Solid-State Circuits Conf., San Francisco, CA, pp.118–119 (1998)Google Scholar
  7. 7.
    Despain, A.M.: Fourier transform computers using CORDIC iterations. IEEE Trans. Comput. 23, 993–1001 (1974)zbMATHCrossRefGoogle Scholar
  8. 8.
    Berkeman, A., Öwall, V., Torkelson, M.: A low logic depth complex multiplier using distributed arithmetic. IEEE J. Solid-State Circuits 35, 656–659 (2000)CrossRefGoogle Scholar
  9. 9.
    Wanhammar, L.: DSP Integrated Circuits. Academic Press, San Diego (1999)Google Scholar
  10. 10.
    Takala, J., Järvinen, T.: Stride permutation access in interleaved memory systems. In: Bhattacharyya, S.S., Deprettere, E.F., Teich, J. (eds.) Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation, pp. 63–84. Marcel Dekker, New York (2004)Google Scholar
  11. 11.
    Wenzler, A., Lüder, E.: New structures for complex multipliers and their noise analysis. In: Proc. IEEE ISCAS, Seattle, WA, vol. 2, pp. 1432–1435 (1995)Google Scholar
  12. 12.
    White, S.A.: A simple FFT butterfly arithmetic unit. IEEE Trans. Circuits Syst. 28, 352–355 (1981)CrossRefGoogle Scholar
  13. 13.
    Chu, E., George, A.: Inside the FFT Black Box: Serial and Parallel Fast Fourier- Transform Algorithms. CRC Press, Boca Raton (2000) Google Scholar
  14. 14.
    Hasan, M., Arslan, T.: FFT coefficient memory reduction technique for OFDM applications. In: Proc. IEEE ICASSP, Orlando, FL, vol. 1, pp. 1085–1088 (2002)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Jarmo Takala
    • 1
  • Konsta Punkka
    • 1
  1. 1.Tampere University of TechnologyTampereFinland

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