Self-loop Pipelining and Reconfigurable Dataflow Arrays

  • João M. P. Cardoso
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3133)


This paper presents some interesting concepts of static dataflow machines that can be used by reconfigurable computing architectures. We introduce some data-driven reconfigurable arrays and summarize techniques to map imperative software programs to those architectures, some of them being focus of current research work. In particular, we briefly present a novel technique for pipelining loops. Experiments with the technique confirm important improvements over the use of conventional loop pipelining. Hence, the technique proves to be an efficient approach to map loops to coarse-grained reconfigurable architectures employing a static dataflow computational model.


Control Token Array Architecture Reconfigurable Architecture Centralize Control Unit Reconfigurable Computing 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • João M. P. Cardoso
    • 1
    • 2
  1. 1.Faculty of Sciences and TechnologyUniversity of AlgarveFaroPortugal
  2. 2.INESC-IDLisbonPortugal

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