Register-Based Permutation Networks for Stride Permutations
In several digital signal processing algorithms, intermediate results between computational stages are reordered according to stride permutations. If such algorithms are computed in parallel with reduced number of processing elements where one element computes several computational nodes, the permutation, instead of being hardwired, requires a storage of intermediate data elements. In this paper, register-based permutation networks for stride permutations are proposed. The proposed networks are regular and scalable and they support any stride of power-of-two. In addition, the networks reach the minimum of register complexity, i.e., the number of registers, indicating area-efficiency.
KeywordsTiming Diagram Very Large Scale Integration Matrix Transpose Register Allocation Fast Fourier Trans
Unable to display preview. Download preview PDF.
- 9.Carlach, J.C., Penard, P., Sicre, J.L.: TCAD: a 27 MHz 8 × 8 discrete cosine transform chip. In: Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing. Glasgow, UK, May 23–26, pp. 2429–2432 (1989)Google Scholar
- 10.Takala, J., Järvinen, T.: Multi-port interconnection networks for matrix transpose. In: Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Phoenix, AZ, U.S.A., May 26–29, pp. 874–877 (2002)Google Scholar
- 11.Takala, J., Järvinen, T., Salmela, P., Akopian, D.: Multi-port interconnection networks for radix-r algorithms. In: Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Salt Lake City, UT, U.S.A, May 7–11, pp. 1177–1180 (2001)Google Scholar