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Synthesis of Asynchronous Hardware from Petri Nets

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Lectures on Concurrency and Petri Nets (ACPN 2003)

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Abstract

As semiconductor technology strides towards billions of transistors on a single die, problems concerned with deep sub-micron process features and design productivity call for new approaches in the area of behavioural models. This paper focuses on some of recent developments and new opportunities for Petri nets in designing asynchronous circuits such as synthesis of asynchronous control circuits from large Petri nets generated from front-end specifications in hardware description languages. These new methods avoid using full reachability state space for logic synthesis. They include direct mapping of Petri nets to circuits, structural methods with linear programming, and synthesis from unfolding prefixes using SAT solvers.

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Authors and Affiliations

  1. Universitat Politècnica de Catalunya, Barcelona, Spain

    Josep Carmona & Jordi Cortadella

  2. University of Newcastle, Newcastle upon Tyne, NE1 7RU, UK

    Victor Khomenko & Alex Yakovlev

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  1. Josep Carmona
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  2. Jordi Cortadella
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  1. Department of Applied Computer Science, Catholic University of Eichstätt-Ingolstadt,  

    Jörg Desel

  2. Institut für Informatik, Humboldt-Universität zu Berlin, Unter den Linden 6, 10099, Berlin, Germany

    Wolfgang Reisig

  3. , Leiden Center of Advanced Computer Science (LIACS), Leiden University, Niels Bohrweg 1, 2333, Leiden, CA, The Netherlands

    Grzegorz Rozenberg

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Carmona, J., Cortadella, J., Khomenko, V., Yakovlev, A. (2004). Synthesis of Asynchronous Hardware from Petri Nets. In: Desel, J., Reisig, W., Rozenberg, G. (eds) Lectures on Concurrency and Petri Nets. ACPN 2003. Lecture Notes in Computer Science, vol 3098. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-27755-2_9

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