Parallel Modular Multiplication Algorithm in Residue Number System

  • Hyun-Sung Kim
  • Hee-Joo Park
  • Sung-Ho Hwang
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3019)

Abstract

This paper presents a novel method for the parallelization of the modular multiplication algorithm in the Residue Number System (RNS). The proposed algorithm executes modular reductions using a new lookup table along with the Mixed Radix number System (MRS) and RNS. MRS is used because algebraic comparison is difficult in RNS, which has a non-weighted number representation. Compared with the previous algorithm, the proposed algorithm only requires L moduli which is half the number needed in the previous algorithm. Furthermore, the proposed algorithm reduces the number of MUL operations by 25 %.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Diffie, W., Hellman, M.: New Directions in Cryptography. IEEE Trans. on Info. Theory IT-22(6), 644–654 (1976)CrossRefMathSciNetGoogle Scholar
  2. 2.
    Szabo, N.S., Tanaka, R.I.: Residue Arithmetic and Its Applications to Computer Technology. McGraw-Hill, New York (1967)MATHGoogle Scholar
  3. 3.
    Taylor, F.J.: Residue Arithmetic: A Tutorial with Examples. Computer, 50–62 (May 1984)Google Scholar
  4. 4.
    Elleithy, K.M., Bayoumi, M.A.: A Systolic Architecture for Modulo Multiplication. IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing 42(11), 725–729 (1995)CrossRefGoogle Scholar
  5. 5.
    Bajard, J.C., Didier, L.S., Kornerup, P.: An RNS Montgomery Modular Multiplication Algorithm. IEEE Trans. on Computers 47(7), 766–776 (1998)CrossRefMathSciNetGoogle Scholar
  6. 6.
    Radhakrishnan, D., Yuan, Y.: Novel Approaches to the Design of VLSI RNS Multipliers. IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing 39(1), 52–57 (1992)MATHCrossRefGoogle Scholar
  7. 7.
    Alia, G., Martinelli, E.: A VLSI Modulo m Multiplier. IEEE Trans. on Computers 40(7), 873–878 (1991)CrossRefGoogle Scholar
  8. 8.
    Taylor, F.J.: A VLSI Residue Arithmetic Multiplier. IEEE Trans. on Computers C-31(6), 540–546 (1982)CrossRefGoogle Scholar
  9. 9.
    Jullien, G.A.: Implementation of Multiplication, Modulo a Prime Number, with Applications to Number Theoretic Transforms. IEEE Trans. on Computers C-29(10), 899–905 (1980)CrossRefGoogle Scholar
  10. 10.
    Soderstrand, M., Jenkins, W.K., Jullian, G.A., Taylor, F.J.: Residue Number Systems: Modern Applications in Digital Signal Processing. IEEE, New York (1986)MATHGoogle Scholar
  11. 11.
    Dimitrov, V.S., Jullien, G.A., Miller, W.C.: A Residue Number System Implementation of Real Orthogonal Transforms. IEEE Trans. on Signal Processing 46(3), 563–570 (1998)CrossRefMathSciNetGoogle Scholar
  12. 12.
    Kim, H.S., Lee, S.W., Yoo, K.Y.: Partitioned Systolic Multiplier for GF(2m). Information Processing Letter 76, 135–139 (2000)CrossRefMathSciNetGoogle Scholar
  13. 13.
    Kim, H.S.: Bit-Serial AOP Arithmetic Architecture for Modular Exponentiation, Ph. D. Thesis, Kyungpook National Univ. (2002)Google Scholar
  14. 14.
    Halbutogullari, A., Koc, C.K.: Parallel Multiplication in GF(2k) using Polynomial Residue Arithmetic. Design, Codes and Cryptography 20(2), 155–173 (2000)MATHCrossRefMathSciNetGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2004

Authors and Affiliations

  • Hyun-Sung Kim
    • 1
  • Hee-Joo Park
    • 1
  • Sung-Ho Hwang
    • 2
  1. 1.Computer EngineeringKyungil UniversityKyungsansiKorea
  2. 2.Dept. of Computer Eng. and SciPohang University of Sci. and TechPohangsiKorea

Personalised recommendations