A Hierarchy Preserving Hierarchical Bottom-Up 2-layer Wiring Algorithm with Respect to Via Minimization

Abstract

Here, the following hierarchical constrained via minimization problem (HCVM) is examined: “Let Q be a circuit with a given layout hierarchy. Find a 2-layer wiring of Q which needs a number of vias minimal with respect to the preservation of hierarchy, i.e., on condition that the description of the result is (nearly) as short as the description of Q before the 2-layer wiring”. The problem arises in connection with hierarchical physical synthesis, which is not highly developed yet although absolutely essential for the design of ULSI circuits. The computational complexity of HCVM is unknown till today. This paper presents a hierarchical bottom-up algorithm to (a variant of) this problem which is locally optimal, i.e., given the 2-layer wirings of the subcircuits of level i, it computes the optimal (partially induced by the wirings of the subcircuits) 2-layer wiring of the circuits of level i + 1. The algorithm’s running time is O(n ³ ) where n is the size of the hierarchical description of Q.