Abstract
Performance optimization, i.e. the problem of finding an optimal investment of transistor area which meets given delay constraints, is considered from an abstract, cell based point of view which allows only solutions within a discrete solution space of coarse granularity. The main advantages of this problem formulation are the independence of the methods from concrete delay modelling (and thus from technology) and the applicability to even very restrictive design styles (as for example gate arrays or sea of gates). Our approach can be considered as a discrete version of the transistor sizing problem on one hand and generalizes to the library mapping problem on the other hand. The paper presents optimal dynamic programming algorithms for trees and heuristics together with first experimental results for general combinational circuits.
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© 1992 B. G. Teubner Verlagsgesellschaft, Leipzig
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Hinsberger, U., Kolla, R. (1992). Performance Optimization of Combinational Circuits. In: Buchmann, J., Ganzinger, H., Paul, W.J. (eds) Informatik. TEUBNER-TEXTE zur Informatik, vol 1. Vieweg+Teubner Verlag, Wiesbaden. https://doi.org/10.1007/978-3-322-95233-2_11
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DOI: https://doi.org/10.1007/978-3-322-95233-2_11
Publisher Name: Vieweg+Teubner Verlag, Wiesbaden
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