Construction of Bayesian Network Model for Integrated Circuits Parametric Testing

Abstract

The Integrated Circuits manufacturing process is composed by many (around 100) elementary process steps, whose interaction determines the final product performances and quality. To monitor the process elementary devices are tested, so to obtain their structural and/or electrical parameters. One aim of this testing phase is to have a feedback on the production line when some problem occurs. This task should determine which particular elementary step is the cause of the problem. Therefore it is necessary to have cause-effect models, so to relate problems to structural parameter instabilities. Once the structural cause is determined, it is generally easy for the engineer to associate it to a precise process step. The methodology we propose in order to diagnose quality loss causes is based upon particular cause-effect structures named Bayesian networks.