Formal Verification of Approximate Sequential Circuits

Abstract

The second part of the formal verification problem is related to the algorithms and techniques for sequential approximated circuits. This chapter explains the methodologies for verification of such circuits. The approximation miter concept introduced in the previous chapter is generalized to include the state relationship of sequential circuits. To the best of our knowledge, very few formal verification techniques have been proposed before for the verification of approximate sequential circuits. The most closely related one to our work is the ASLAN framework, which employs a user-specified quality evaluation circuit in the form of a test bench. However, this is a semi-automated approach, since the user has to design the quality evaluation circuit and provide as an input to the ASLAN framework. This requires a detailed understanding of the design concepts along with a sound knowledge on formal property checking (e.g., specification of a liveness property). On the contrary, our approach is fully automated. Furthermore, the case studies provided later in this chapter show that the error analysis of the approximate sequential circuits can lead to a different conclusion altogether, when compared with the analysis of combinational circuits in isolation.