Skip to main content
SpringerLink
Log in

Test Generation and Lightweight Checking for Multi-core Memory Consistency

  • Chapter
  • First Online:
Post-Silicon Validation and Debug

  • 1071 Accesses

Abstract

In this book chapter, we introduce a post-silicon validation solution for multi-core memory consistency. We first introduce several memory consistency models widely used in modern multi-core microprocessors, and explain memory consistency validation efforts in the literature. We then present MTraceCheck, our post-silicon memory consistency validation framework. MTraceCheck is based on a constrained-random testing approach that generates many constrained-random test programs designed to stress-test a variety of memory-access interleaving behaviors across multiple cores. We instrument the generated tests with our novel observability-enhancing code, which computes a compact signature representing the memory-access interleaving patterns observed during the test execution. The instrumented tests are then repeatedly run to exhibit subtle memory ordering behaviors, and we gather a collection of signatures from the repeated runs. Finally, we apply a novel efficient checking algorithm to detect any consistency violation from the collection of signatures. We evaluate MTraceCheck on two platforms: an x86-based desktop and an ARM-based single-board computer. Compared to a conventional memory-tracking method, we significantly reduce memory operations introduced for the purpose of verification by 93% on average. In addition, we reduce the checking computation requirements by 81% on average, compared to a conventional checking algorithm. We also demonstrate that MTraceCheck can detect subtle bugs in a full-system simulator.

This work is based on an earlier work: “MTraceCheck: Validating Non-Deterministic Behavior of Memory Consistency Models in Post-Silicon Validation” by Doowon Lee and Valeria Bertacco in the 44th Annual International Symposium on Computer Architecture (ISCA ’17) ©ACM 2017. https://doi.org/10.1145/3079856.3080235.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 89.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 119.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    The signature-sorting time can be significantly reduced by two optimizations: (1) the sorting routine can utilize multiple cores available, and (2) the sorting routine can be run on the more powerful Cortex-A15 cluster. These two are not implemented in our experimental evaluations.

References

  1. A. Adir, M. Golubev, S. Landa, A. Nahir, G. Shurek, V. Sokhin, A. Ziv, Threadmill: a post-silicon exerciser for multi-threaded processors, in Proceedings of the 48th Design Automation Conference (2011), pp. 860–865. https://doi.org/10.1145/2024724.2024916

  2. S.V. Adve, K. Gharachorloo, Shared memory consistency models: a tutorial. Computer 29(12), 66–76 (1996). https://doi.org/10.1109/2.546611

    Article  Google Scholar 

  3. J. Alglave, A formal hierarchy of weak memory models. Form. Methods Syst. Design 41(2), 178–210 (2012). https://doi.org/10.1007/s10703-012-0161-5

    Article  MATH  Google Scholar 

  4. J. Alglave, L. Maranget, S. Sarkar, P. Sewell, Fences in weak memory models, in Computer Aided Verification: 22nd International Conference, CAV 2010 (2010), pp. 258–272. https://doi.org/10.1007/978-3-642-14295-6_25

  5. J. Alglave, L. Maranget, S. Sarkar, P. Sewell, Litmus: running tests against hardware, in Tools and Algorithms for the Construction and Analysis of Systems: 17th International Conference, TACAS 2011 (2011), pp. 41–44. https://doi.org/10.1007/978-3-642-19835-9_5

  6. J. Alglave, L. Maranget, M. Tautschnig, Herding cats: modelling, simulation, testing, and data mining for weak memory. ACM Trans. Program. Lang. Syst. 36(2), 7:1–7:74 (2014). https://doi.org/10.1145/2627752

    Article  Google Scholar 

  7. ARM: Barrier Litmus Tests and Cookbook (2009)

    Google Scholar 

  8. ARM: Cortex-A9 MPCore Programmer Advice Notice Read-after-Read Hazards, ARM Reference 761319 (2011)

    Google Scholar 

  9. ARM: Embedded Trace Macrocell Architecture Specification (2011)

    Google Scholar 

  10. ARM: ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition (2012)

    Google Scholar 

  11. ARM: ARM Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile (2017)

    Google Scholar 

  12. Arvind, J.W. Maessen, Memory model \(=\) instruction reordering \(+\) store atomicity, in Proceedings of the 33rd Annual International Symposium on Computer Architecture (2006), pp. 29–40. https://doi.org/10.1109/ISCA.2006.26

  13. T. Ball, J.R. Larus, Efficient path profiling, in Proceedings of the 29th Annual ACM/IEEE International Symposium on Microarchitecture (1996), pp. 46–57. https://doi.org/10.1109/MICRO.1996.566449

  14. N. Binkert, B. Beckmann, G. Black, S.K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D.R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M.D. Hill, D.A. Wood, The gem5 simulator. ACM SIGARCH Comput. Archit. News 39(2), 1–7 (2011). https://doi.org/10.1145/2024716.2024718

    Article  Google Scholar 

  15. H.W. Cain, M.H. Lipasti, R. Nair, Constraint graph analysis of multithreaded programs, in Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (2003), pp. 4–14. https://doi.org/10.1109/PACT.2003.1237997

  16. K. Chen, S. Malik, P. Patra, Runtime validation of memory ordering using constraint graph checking, in 2008 IEEE 14th International Symposium on High Performance Computer Architecture (2008), pp. 415–426. https://doi.org/10.1109/HPCA.2008.4658657

  17. Y. Chen, Y. Lv, W. Hu, T. Chen, H. Shen, P. Wang, H. Pan, Fast complete memory consistency verification, in 2009 IEEE 15th International Symposium on High Performance Computer Architecture (2009), pp. 381–392. https://doi.org/10.1109/HPCA.2009.4798276

  18. T.H. Cormen, C.E. Leiserson, R.L. Rivest, C. Stein, Introduction to Algorithms, 3rd edn. (The MIT Press, Cambridge, 2009)

    MATH  Google Scholar 

  19. Das U-Boot – the universal boot loader (2016), http://www.denx.de/wiki/U-Boot

  20. M. Elver, V. Nagarajan, McVerSi: a test generation framework for fast memory consistency verification in simulation, in 2016 IEEE International Symposium on High Performance Computer Architecture (2016), pp. 618–630. https://doi.org/10.1109/HPCA.2016.7446099

  21. N. Foutris, D. Gizopoulos, M. Psarakis, X. Vera, A. Gonzalez, Accelerating microprocessor silicon validation by exposing ISA diversity, in Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (2011), pp. 386–397. https://doi.org/10.1145/2155620.2155666

  22. gem5 mercurial repository host (2016), http://repo.gem5.org

  23. GNU coreutils version 8.25 (2016), http://ftp.gnu.org/gnu/coreutils

  24. S. Hangal, D. Vahia, C. Manovit, J.Y.J. Lu, S. Narayanan, TSOtool: a program for verifying memory systems using the memory consistency model, in Proceedings of the 31st Annual International Symposium on Computer Architecture (2004), pp. 114–123. https://doi.org/10.1109/ISCA.2004.1310768

  25. IBM: Power ISA Version 2.07B (2015)

    Google Scholar 

  26. Intel: Intel 64 Architecture Memory Ordering White Paper (2007)

    Google Scholar 

  27. Intel: Intel 64 and IA-32 Architectures Software Developer’s Manual (2015)

    Google Scholar 

  28. Intel: 6th Generation Intel Processor Family Specification Update (2016)

    Google Scholar 

  29. k-medoids algorithm (2016), https://en.wikipedia.org/wiki/K-medoids

  30. R. Komuravelli, S.V. Adve, C.T. Chou, Revisiting the complexity of hardware cache coherence and some implications. ACM Trans. Archit. Code Optim. 11(4), 37:1–37:22 (2014). https://doi.org/10.1145/2663345

    Article  Google Scholar 

  31. L. Lamport, How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Trans. Comput. 28(9), 690–691 (1979). https://doi.org/10.1109/TC.1979.1675439

    Article  MATH  Google Scholar 

  32. D. Lee, V. Bertacco, MTraceCheck: validating non-deterministic behavior of memory consistency models in post-silicon validation, in Proceedings of the 44th Annual International Symposium on Computer Architecture (2017), pp. 201–213. https://doi.org/10.1145/3079856.3080235

  33. D. Lin, T. Hong, Y. Li, E. S, S. Kumar, F. Fallah, N. Hakim, D.S. Gardner, S. Mitra, Effective post-silicon validation of system-on-chips using quick error detection. IEEE Trans. Comput. Aided Design Integr. Circuits Syst. 33(10), 1573–1590 (2014). https://doi.org/10.1109/TCAD.2014.2334301

    Article  Google Scholar 

  34. D. Lustig, M. Pellauer, M. Martonosi, PipeCheck: specifying and verifying microarchitectural enforcement of memory consistency models, in Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture (2014), pp. 635–646. https://doi.org/10.1109/MICRO.2014.38

  35. D. Lustig, C. Trippel, M. Pellauer, M. Martonosi, ArMOR: defending against memory consistency model mismatches in heterogeneous architectures, in Proceedings of the 42nd Annual International Symposium on Computer Architecture (2015), pp. 388–400. https://doi.org/10.1145/2749469.2750378

  36. D. Lustig, A. Wright, A. Papakonstantinou, O. Giroux, Automated synthesis of comprehensive memory model litmus test suites, in Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems (2017), pp. 661–675. https://doi.org/10.1145/3037697.3037723

  37. S. Mador-Haim, R. Alur, M.M. Martin, Generating litmus tests for contrasting memory consistency models, in Computer Aided Verification: 22nd International Conference, CAV 2010 (2010), pp. 273–287. https://doi.org/10.1007/978-3-642-14295-6_26

  38. B.W. Mammo, V. Bertacco, A. DeOrio, I. Wagner, Post-silicon validation of multiprocessor memory consistency. IEEE Trans. Comput. Aided Design Integr. Circuits Syst. 34(6), 1027–1037 (2015). https://doi.org/10.1109/TCAD.2015.2402171

    Article  Google Scholar 

  39. Y.A. Manerkar, D. Lustig, M. Martonosi, M. Pellauer, RTLCheck: verifying the memory consistency of RTL designs, in Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture (2017), pp. 463–476. https://doi.org/10.1145/3123939.3124536

  40. A. Meixner, D.J. Sorin, Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures. IEEE Trans. Dependable Secur. Comput. 6(1), 18–31 (2009). https://doi.org/10.1109/TDSC.2007.70243

    Article  Google Scholar 

  41. M. Naylor, S.W. Moore, A. Mujumdar, A consistency checker for memory subsystem traces, in 2016 Formal Methods in Computer-Aided Design (FMCAD) (2016), pp. 133–140. https://doi.org/10.1109/FMCAD.2016.7886671

  42. T. Rabetti, R. Morad, A. Goryachev, W. Kadry, R.D. Peterson, SLAM: SLice And Merge - effective test generation for large systems, in Hardware and Software: Verification and Testing (2013), pp. 151–165

    Google Scholar 

  43. A. Roy, S. Zeisset, C.J. Fleckenstein, J.C. Huang, Fast and generalized polynomial time memory consistency verification, in Computer Aided Verification: 18th International Conference, CAV 2006 (2006), pp. 503–516. https://doi.org/10.1007/11817963_46

  44. E. Seligman, T. Schubert, M.V.A.K. Kumar, Formal Verification (Morgan Kaufmann, San Francisco, 2015)

    Book  Google Scholar 

  45. O. Shacham, M. Wachs, A. Solomatnikov, A. Firoozshahian, S. Richardson, M. Horowitz, Verification of chip multiprocessor memory systems using a relaxed scoreboard, in Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (2008), pp. 294–305. https://doi.org/10.1109/MICRO.2008.4771799

  46. D.J. Sorin, M.D. Hill, D.A. Wood, A Primer on Memory Consistency and Cache Coherence, 1st edn. (Morgan & Claypool Publishers, 2011)

    Google Scholar 

  47. The Coq proof assistant (2016), https://coq.inria.fr

  48. I. Wagner, V. Bertacco, Reversi: Post-silicon validation system for modern microprocessors, in IEEE International Conference on Computer Design (2008), pp. 307–314. https://doi.org/10.1109/ICCD.2008.4751878

  49. A. Waterman, K. Asanovic, SiFive Inc., The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.2 (2017)

    Google Scholar 

  50. D. Weaver, T. Germond, The SPARC Architectural Manual (Version 9) (Prentice-Hall Inc., Englewood Cliffs, 1994)

    Google Scholar 

Download references

Acknowledgements

We would like to thank Prof. Todd Austin, Biruk Mammo, and Cao Gao for their advice and counseling throughout the development of this project. The work was supported in part by C-FAR, one of six centers of STARnet, a Semiconductor Research Corporation program sponsored by MARCO and DARPA. Doowon Lee was also supported by a Rackham Predoctoral Fellowship at the University of Michigan.

Author information

Authors and Affiliations

  1. University of Michigan, 2260 Hayward Street, Ann Arbor, MI, 48109-2121, USA

    Doowon Lee & Valeria Bertacco

Authors
  1. Doowon Lee
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Valeria Bertacco
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Valeria Bertacco .

Editor information

Editors and Affiliations

  1. Department of Computer and Information Science and Engineering, University of Florida, Gainesville, FL, USA

    Prabhat Mishra

  2. Department of Computer and Information Science and Engineering, University of Florida, Gainesville, FL, USA

    Farimah Farahmandi

Rights and permissions

Reprints and permissions

Copyright information

© 2019 Springer Nature Switzerland AG

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Lee, D., Bertacco, V. (2019). Test Generation and Lightweight Checking for Multi-core Memory Consistency. In: Mishra, P., Farahmandi, F. (eds) Post-Silicon Validation and Debug. Springer, Cham. https://doi.org/10.1007/978-3-319-98116-1_9

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-98116-1_9

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-98115-4

  • Online ISBN: 978-3-319-98116-1

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation