High-Level Debugging of Post-Silicon Failures

Abstract

Due to the continuous increase of chip design complexity, some logic design bugs may not be detected by pre-silicon verification efforts, and as a result, post-silicon debugging (verification, analysis, and debugging processes after producing silicon) becomes more and more important, especially from the viewpoint of shorter time to market. In this chapter, we discuss two different issues on dealing with post-silicon failures in relation to high-level designs such as C-based designs. The first one is to partially use programmable circuits, such as LUT (Lookup Table). In order to reduce the time for debugging, partial programmability in silicon is incorporated into our method by adding patchable logic circuits to the original designs. Those partial programmability is used to eliminate the bugs found in post-silicon phases as well as analyzing the bugs. The second one is to reproduce equivalent high-level design descriptions after the post-silicon debugging processes are applied. After debugging in post-silicon, the functionality of the debugged implementation may be different from the original high-level design description, which must be adjusted for documentation purposes as well as keeping the consistency of the designs. We propose a template-based method by which high-level descriptions are automatically generated as modifications of the original high-level descriptions by repeatedly simulating the debugged implementations. The experimental results on several examples demonstrate the effectiveness of the proposed methods.