Architecture Emulation and Simulation of Future Many-Core Epiphany RISC Array Processors

  • David A. Richie
  • James A. Ross
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10861)


The Adapteva Epiphany many-core architecture comprises a scalable 2D mesh Network-on-Chip (NoC) of low-power RISC cores with minimal uncore functionality. The Epiphany architecture has demonstrated significantly higher power-efficiency compared with other more conventional general-purpose floating-point processors. The original 32-bit architecture has been updated to create a 1,024-core 64-bit processor recently fabricated using a 16 nm process. We present here our recent work in developing an emulation and simulation capability for future many-core processors based on the Epiphany architecture. We have developed an Epiphany SoC device emulator that can be installed as a virtual device on an ordinary x86 platform and utilized with the existing software stack used to support physical devices, thus creating a seamless software development environment capable of targeting new processor designs just as they would be interfaced on a real platform. These virtual Epiphany devices can be used for research in the area of many-core RISC array processors in general.


RISC Network-on-Chip Emulation Simulation Epiphany 



This work was supported by the U.S. Army Research Laboratory. The authors thank David Austin Richie for contributions to this work.


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Copyright information

© This is a U.S. government work and its text is not subject to copyright protection in the United States; however, its text may be subject to foreign copyright protection 2018

Authors and Affiliations

  1. 1.Brown Deer TechnologyForest HillUSA
  2. 2.U.S. Army Research LaboratoryAberdeen Proving GroundUSA

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