Abstract
Internet-of-Things end-nodes demand low power processing platforms characterized by heterogeneous dedicated units, controlled by a processor core running multiple control threads. Such architecture scheme fits one of the main target application domain of the RISC-V instruction set. We present an open-source processing core compliant with RISC-V on the software side and with the popular Pulpino processor platform on the hardware side, while supporting interleaved multi-threading for IoT applications. The latter feature is a novel contribution in this application domain. We report details about the microarchitecture design along with performance data.
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Cheikh, A., Cerutti, G., Mastrandrea, A., Menichelli, F., Olivieri, M. (2019). The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes. In: De Gloria, A. (eds) Applications in Electronics Pervading Industry, Environment and Society. ApplePies 2017. Lecture Notes in Electrical Engineering, vol 512. Springer, Cham. https://doi.org/10.1007/978-3-319-93082-4_12
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DOI: https://doi.org/10.1007/978-3-319-93082-4_12
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