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Boosting Transactional Memory with Stricter Serializability

  • Pierre Sutra
  • Patrick Marlier
  • Valerio Schiavoni
  • François Trahay
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10852)

Abstract

Transactional memory (TM) guarantees that a sequence of operations encapsulated into a transaction is atomic. This simple yet powerful paradigm is a promising direction for writing concurrent applications. Recent TM designs employ a time-based mechanism to leverage the performance advantage of invisible reads. With the advent of many-core architectures and non-uniform memory (NUMA) architectures, this technique is however hitting the synchronization wall of the cache coherency protocol. To address this limitation, we propose a novel and flexible approach based on a new consistency criteria named stricter serializability (\({\text {SSER}^+}\)). Workloads executed under \({\text {SSER}^+}\) are opaque when the object graph forms a tree and transactions traverse it top-down. We present a matching algorithm that supports invisible reads, lazy snapshots, and that can trade synchronization for more parallelism. Several empirical results against a well-established TM design demonstrate the benefits of our solution.

Keywords

Transactional memory NUMA Stricter serializability 

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Copyright information

© IFIP International Federation for Information Processing 2018

Authors and Affiliations

  1. 1.University of NeuchâtelNeuchâtelSwitzerland
  2. 2.Télécom SudParisÉvryFrance

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