Abstract
In this chapter, a second design example is presented. The considered circuit is a 16-to-1 multiplexer, optimized for high-speed operation. The circuit is designed in a 90 nm CMOS technology, and compared against a CMOS standard-cell implementation.
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Badel, S., Baltaci, C., Cevrero, A., Leblebici, Y. (2019). Design Example II: High-Speed Multiplexer. In: Design Automation for Differential MOS Current-Mode Logic Circuits . Springer, Cham. https://doi.org/10.1007/978-3-319-91307-0_7
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DOI: https://doi.org/10.1007/978-3-319-91307-0_7
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Publisher Name: Springer, Cham
Print ISBN: 978-3-319-91306-3
Online ISBN: 978-3-319-91307-0
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