Abstract
FinFET/SRAM has been contributing to the new evolution of modern-day memory units that are used over broader scale of computing units and other sophisticated devices. A review analysis is performed over existing system to find that existing approaches are more inclined towards improvement in performance parameters and very less towards design optimization. Hence, a novel approach is introduced and is named as Search Optimization based Predictive Approach (SOPA) for optimizing the design structure of FinFET/SRAM so that it can ensure highest degree of fault tolerance when used in broader scale of dynamic applications and modern computing devices. In this, analytical methodology used where the proposed computational model is found to offer reduced computational time and more yield in increasing simulation iteration. The study contributes to progressive convergence of elite design of FinFET/SRAM rather than recursive design and hence cost effective.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Wicht, B.: Current Sense Amplifiers for Embedded SRAM in High-Performance System-on-a-Chip Designs. Springer, Heidelberg (2013)
Alioto, M.: Enabling the Internet of Things: From Integrated Circuits to Integrated Systems. Springer, Cham (2017)
Sun, G.: Exploring Memory Hierarchy Design with Emerging Memory Technologies. Springer, Cham (2013)
Dasgupta, S., Kaushik, B.K., Kumar Pal, P.: Spacer Engineered FinFET Architectures: High-Performance Digital Circuit Applications. CRC Press, Boca Raton (2017)
Reis, R., Cao, Y., Wirth, G.: Circuit Design for Reliability. Springer, New York (2015)
Gildenblat, G.: Compact Modeling: Principles, Techniques and Applications. Springer, Dordrecht (2010)
Chauhan, Y.S., Lu, D.D., Sriramkumar, V., Khandelwal, S.: FinFET Modeling for IC Simulation and Design: Using the BSIM-CMG Standard. Academic Press, London (2015)
Weste, N.H.E., Harris, D.: CMOS VLSI Design: A Circuits and Systems Perspective. Pearson Education India (2015)
Girish, H., Shashikumar, D.R.: Insights of performance enhancement techniques on FinFET-based SRAM cells. Commun. Appl. Electron. (CAE) 5(6), 20–26 (2016)
Girish, H., Shashikumar, D.R.: Cost-effective computational modeling of fault tolerant optimization of FinFET-Based SRAM cells. In: Computer Science On-line Conference, pp. 1–12. Springer (2017)
Bhattacharya, D., Jha, N.K.: Ultra-high density monolithic 3-D FinFET SRAM with enhanced read stability. IEEE Trans. Circ. Syst. I Regul. Pap. 63(8), 1176–1187 (2016)
Fang, Y.P., Oates, A.S.: Characterization of single bit and multiple cell soft error events in planar and FinFET SRAMs. IEEE Trans. Device Mater. Reliab. 16(2), 132–137 (2016)
Chen, Y.H., et al.: A 16 nm 128 Mb SRAM in High-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications. IEEE J. Solid State Circ. 50(1), 170–177 (2015)
Yang, Y., Park, J., Song, S.C., Wang, J., Yeap, G., Jung, S.O.: Single-ended 9T SRAM cell for near-threshold voltage operation with enhanced read performance in 22-nm FinFET technology. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23(11), 2748–2752 (2015)
Karl, E., et al.: A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS technology with capacitive charge-sharing write assist circuitry. IEEE J. Solid State Circ. 51(1), 222–229 (2016)
Zhang, X., Connelly, D., Takeuchi, H., Hytha, M., Mears, R.J., Liu, T.J.K.: Comparison of SOI versus bulk FinFET technologies for 6T-SRAM voltage scaling at the 7-/8-nm node. IEEE Trans. Electron Devices 64(1), 329–332 (2017)
Kulkarni, J.P., et al.: 5.6 Mb/mm2 1R1 W 8T SRAM arrays operating down to 560 mV utilizing small-signal sensing with charge shared bitline and asymmetric sense amplifier in 14 nm FinFET CMOS technology. IEEE J. Solid State Circ. 52(1), 229–239 (2017)
Hu, V.P.H., Fan, M.L., Su, P., Chuang, C.T.: Analysis of GeOI FinFET 6T SRAM cells with variation-tolerant WLUD read-assist and TVC write-assist. IEEE Trans. Electron Devices 62(6), 1710–1715 (2015)
Bhattacharya, D., Jha, N.K.: TCAD-assisted capacitance extraction of FinFET SRAM and logic arrays. IEEE Trans. Very Large Scale Integr. VLSI Syst. 24(1), 329–333 (2016)
Song, T., et al.: A 10 nm FinFET 128 Mb SRAM With assist adjustment system for power, performance, and area optimization. IEEE J. Solid State Circ. 52(1), 240–249 (2017)
Mishra, S., Mahapatra, S.: On the impact of time-zero variability, variable NBTI, and stochastic TDDB on SRAM cells. IEEE Trans. Electron Devices 63(7), 2764–2770 (2016)
Asenov, A., et al.: Variability aware simulation based Design-Technology Cooptimization (DTCO) Flow in 14 nm FinFET/SRAM cooptimization. IEEE Trans. Electron Devices 62(6), 1682–1690 (2015)
Joshi, R., et al.: A universal hardware-driven PVT and layout-aware predictive failure analytics for SRAM. IEEE Trans. Very Large Scale Integr. VLSI Syst. 24(3), 968–978 (2016)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer International Publishing AG, part of Springer Nature
About this paper
Cite this paper
Girish, H., Shashikumar, D.R. (2019). SOPA: Search Optimization Based Predictive Approach for Design Optimization in FinFET/SRAM. In: Silhavy, R. (eds) Artificial Intelligence and Algorithms in Intelligent Systems. CSOC2018 2018. Advances in Intelligent Systems and Computing, vol 764. Springer, Cham. https://doi.org/10.1007/978-3-319-91189-2_3
Download citation
DOI: https://doi.org/10.1007/978-3-319-91189-2_3
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-91188-5
Online ISBN: 978-3-319-91189-2
eBook Packages: Intelligent Technologies and RoboticsIntelligent Technologies and Robotics (R0)