Design and Development of Stress-Engineered Compliant Interconnect for Microelectronic Packaging

Abstract

Power and latency are fast becoming major bottlenecks in the design of high-performance microprocessors and computers. Power relates to both consumption and dissipation, and therefore, effective power distribution design and thermal management solutions are required. Latency is caused by the global interconnects on the IC (integrated circuit) that span at least half a chip edge due to the RC (resistance-capacitance) and transmission line delay [1]. Limits to chip power dissipation and power density and limits on hyper-pipelining in microprocessors threaten to impede the exponential growth in microprocessor performance. In contrast, multi-core processors can continue to provide a historical performance growth on most consumer and business applications provided that the power efficiency of the cores stays within reasonable power budgets. To sustain the dramatic performance growth, a rapid increase in the number of cores per die and a corresponding growth in off-chip bandwidth are required [2]. Thus, it is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors (ITRS) that by the year 2018, with the IC node size shrinking to 22 nm by 2016 and 14 nm by 2020, the chip-to-substrate area array input-output interconnects will require a pitch of 70 μm [3]. Furthermore, to reduce the RC and transmission line delay, low-K dielectric/Cu and ultra-low-K dielectric/Cu interconnects on silicon will become increasingly common. In such ICs, the thermomechanical stresses induced by the chip-to-substrate interconnects could crack or delaminate the dielectric material causing reliability problems (Table 28.1).