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Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays

  • Éricles Sousa
  • Frank Hannig
  • Jürgen Teich
Conference paper
Part of the IFIP Advances in Information and Communication Technology book series (IFIPAICT, volume 523)

Abstract

Coarse-Grained Reconfigurable Arrays (CGRAs) have emerged as a powerful solution to speedup computationally intensive applications. Heterogeneous MPSoC architectures containing such reconfigurable accelerators have the advantage of providing high flexibility, power-efficiency, and high performance. However, CGRAs may suffer from a data access bottleneck. To mitigate this problem, we present a reconfigurable buffer architecture for CGRAs. Here, the buffers can be configured at runtime to select between different schemes for memory access, i.e., addressable RAMs or pixel buffers. We showcase the benefits of our approach by prototyping a heterogeneous MPSoC architecture containing a RISC processor and a class of CGRA called Tightly Coupled Processor Arrays (TCPAs). The architecture is prototyped in FPGA technology. For basic image processing algorithms, we demonstrate that our proposed buffer structures for system integration allow to increase the memory bandwidth utilization and allow for a performance improvement of up to 7% in comparison to state-of-the-art solutions for image processing.

Notes

Acknowledgment

This work was supported by the German Research Foundation (DFG) as part of the Transregional Collaborative Research Centre “Invasive Computing” (SFB/TR 89) and Research Training Group 1773 “Heterogeneous Image Systems”. The first author is also grateful to the Brazilian National Council for Scientific and Technological Development (CNPq) for supporting his research.

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Copyright information

© IFIP International Federation for Information Processing 2017

Authors and Affiliations

  1. 1.Hardware/Software Co-design, Department of Computer ScienceFriedrich-Alexander-Universität Erlangen-Nürnberg (FAU)ErlangenGermany

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