Low Latency FPGA Implementation of Izhikevich-Neuron Model

  • Vitor Bandeira
  • Vivianne L. Costa
  • Guilherme Bontorin
  • Ricardo A. L. Reis
Conference paper
Part of the IFIP Advances in Information and Communication Technology book series (IFIPAICT, volume 523)


The Izhikevich’s simple model (ISM) for neural activity presents a good compromise between waveform quality and computational cost. FPGAs (Field Programmable Gate Array) are powerful, flexible, and inexpensive digital hardware that can implement such model. In this paper, we present a highly combinational, low latency implementation of ISM for FPGA. In the absence of official benchmark to compare different implementations, we propose two different metrics to compare the technical literature with our implementation. In this benchmark, we can implement a system that, when compared to the literature, has almost 1.5 times the number of digital neurons (DN), and latency more than 56 times smaller. This shows that our implementation is best suited for hybrid network systems and presents a fair performance for only-artificial networks.



This work is funded by the following agencies: Federal Agency for Support and Evaluation of Higher Education of Brazil (CAPES), the National Council for Technological and Scientific Development (CNPq), and the Foundation for Research of the State of Rio Grande do Sul (FAPERGS). The authors thank the Macnica-DHW Ltda for the FPGAs boards and technical support.


  1. 1.
    Ambroise, M., Levi, T., Bornat, Y., Saighi, S.: Biorealistic spiking neural network on FPGA. In: 47th Annual Conference on Information Sciences and Systems (CISS), pp. 1–6, March 2013Google Scholar
  2. 2.
    Bontorin, G., Renaud, S., Garenne, A., Alvado, L., Le Masson, G., Tomas, J.: A real-time closed-loop setup for hybrid neural networks. In: 29th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBS 2007, pp. 3004–3007, August 2007Google Scholar
  3. 3.
    Burden, R.L., Faires, J.D.: Numerical Analysis, 9th edn. Brooks/Cole Publishing Company, Boston (2011)zbMATHGoogle Scholar
  4. 4.
    Cassidy, A., Andreou, A.: Dynamical digital silicon neurons. In: IEEE Biomedical Circuits and Systems Conference, BioCAS 2008, pp. 289–292, November 2008Google Scholar
  5. 5.
    Cassidy, A., Denham, S., Kanold, P., Andreou, A.: FPGA based silicon spiking neural array. In: IEEE Biomedical Circuits and Systems Conference, BIOCAS 2007, pp. 75–78, November 2007Google Scholar
  6. 6.
    Cheung, K., Schultz, S., Leong, P.: A parallel spiking neural network simulator. In: International Conference on Field-Programmable Technology, FPT 2009, pp. 247–254, December 2009Google Scholar
  7. 7.
    Indiveri, G., Horiuchi, T.K.: Frontiers in neuromorphic engineering. Front. Neurosci. 5, 118 (2011)Google Scholar
  8. 8.
    Izhikevich, E.M.: Neural excitability, spiking and bursting. Int. J. Bifurcat. Chaos 10(6), 1171–1266 (2000)MathSciNetCrossRefGoogle Scholar
  9. 9.
    Izhikevich, E.M.: Simple model of spiking neurons. IEEE 14, 1569–1572 (2003)Google Scholar
  10. 10.
    Rice, K.L., Bhuiyan, M., Taha, T., Vutsinas, C.N., Smith, M.: FPGA implementation of Izhikevich spiking neural networks for character recognition. In: International Conference on Reconfigurable Computing and FPGAs. ReConFig 2009, pp. 451–456, December 2009Google Scholar
  11. 11.
    Thomas, D.B., Luk, W.: FPGA accelerated simulation of biologically plausible spiking neural networks. In: Pocek, K.L., Buell, D.A. (eds.) FCCM, pp. 45–52. IEEE Computer Society (2009)Google Scholar
  12. 12.
    Wennberg, R., Velazquez, J.L.P.: Coordinated Activity in the Brain: Measurements and Relevance to Brain Function and Behavior. Springer, New York (2009). Scholar

Copyright information

© IFIP International Federation for Information Processing 2017

Authors and Affiliations

  1. 1.Universidade Federal do Rio Grande do Sul PGMicro/PPGC – Instituto de InformáticaPorto AlegreBrazil
  2. 2.Universidade Federal do Paraná PPGMNECuritibaBrazil

Personalised recommendations