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Low Latency FPGA Implementation of Izhikevich-Neuron Model

  • Vitor Bandeira
  • Vivianne L. Costa
  • Guilherme Bontorin
  • Ricardo A. L. Reis
Conference paper
Part of the IFIP Advances in Information and Communication Technology book series (IFIPAICT, volume 523)

Abstract

The Izhikevich’s simple model (ISM) for neural activity presents a good compromise between waveform quality and computational cost. FPGAs (Field Programmable Gate Array) are powerful, flexible, and inexpensive digital hardware that can implement such model. In this paper, we present a highly combinational, low latency implementation of ISM for FPGA. In the absence of official benchmark to compare different implementations, we propose two different metrics to compare the technical literature with our implementation. In this benchmark, we can implement a system that, when compared to the literature, has almost 1.5 times the number of digital neurons (DN), and latency more than 56 times smaller. This shows that our implementation is best suited for hybrid network systems and presents a fair performance for only-artificial networks.

Notes

Acknowledgment

This work is funded by the following agencies: Federal Agency for Support and Evaluation of Higher Education of Brazil (CAPES), the National Council for Technological and Scientific Development (CNPq), and the Foundation for Research of the State of Rio Grande do Sul (FAPERGS). The authors thank the Macnica-DHW Ltda for the FPGAs boards and technical support.

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Copyright information

© IFIP International Federation for Information Processing 2017

Authors and Affiliations

  1. 1.Universidade Federal do Rio Grande do Sul PGMicro/PPGC – Instituto de InformáticaPorto AlegreBrazil
  2. 2.Universidade Federal do Paraná PPGMNECuritibaBrazil

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