Modeling and Analysis of SLDL-Captured NoC Abstractions

  • Ran Hao
  • Nasibeh Teimouri
  • Kasra Moazzemi
  • Gunar Schirner
Conference paper
Part of the IFIP Advances in Information and Communication Technology book series (IFIPAICT, volume 523)


With increasing number of IP cores, parallel communication architectures including NoCs have emerged for many-core systems. To efficiently architect NoCs, early analysis of crucial run-time metrics such as throughput, latency and saturation time is required. This requires abstract modeling of NoCs. Modeling abstraction, and consequently the modeling granularity impacts the accuracy and speed of simulation. While a fine-grained model will slowly lead more accurate information, a coarser model simulates faster and yields less accurate predictions. This paper first identifies possible levels of abstraction for NoC models and correlating captured features with the accuracy/speed trade-off. Second, this paper proposes two NoC models at different abstraction levels: a finer grained Bus-Functional Model (BFM), and a coarser Transaction-Level Model (TLM). The BFM updates the system status after any events happening during data unit transmission, while the TLM updates the system status at the end of data unit transmission.

Our evaluation results show moving to higher abstraction (from BFM to TLM) gains 10x to 50x speedup at the cost of 10%–20% accuracy loss on average. Our analysis approach and results guide system architects in exploring NoC architectural alternatives and help identifying suitable abstract levels.


  1. 1.
    Sgroi, M., Sheets, M., Mihal, A., Keutzer, K., Malik, S., Rabaey, J., Sangiovanni-Vencentelli, A.: Addressing the system-on-a-chip interconnect woes through communication-based design. In: Design Automation Conference (DAC), pp. 667–672. ACM (2001)Google Scholar
  2. 2.
    Owens, J., Dally, W., Ho, R., Jayasimha, D.N., Keckler, S., Peh, L.-S.: Research challenges for on-chip interconnection networks. Micro IEEE 27(5), 96–108 (2007)CrossRefGoogle Scholar
  3. 3.
    Dally, W., Towles, B.: Route packets, not wires: on-chip interconnection networks. In: Design Automation Conference (DAC), pp. 684–689 (2001)Google Scholar
  4. 4.
    Moraes, F., Calazans, N., Mello, A., Möller, L., Ost, L.: HERMES: an infrastructure for low area overhead packet-switching networks on chip. Integr. VLSI J. 38(1), 69–93 (2004)Google Scholar
  5. 5.
    Foroutan, S., Thonnart, Y., Hersemeule, R., Jerraya, A.: An analytical method for evaluating Network-on-Chip performance. In: Design, Automation Test in Europe (DATE), pp. 1629–1632 (2010)Google Scholar
  6. 6.
    Schirner, G., Dömer, R.: Abstract communication modeling: a case study using the CAN automotive bus. In: Rettberg, A., Zanella, M.C., Rammig, F.J. (eds.) From Specification to Embedded Systems Application. IFIPAICT, vol. 184, pp. 189–200. Springer, Heidelberg (2005).
  7. 7.
    Schirner, G., Dömer, R.: Quantitative analysis of transaction level models for the AMBA bus. In: Design, Automation and Test in Europe (DATE), vol. 1, pp. 1–6 (2006)Google Scholar
  8. 8.
    Lu, K., Muller-Gritschneder, D., Schlichtmann, U.: Accurately timed transaction level models for virtual prototyping at high abstraction level. In: Design, Automation Test in Europe Conference Exhibition (DATE), pp. 135–140 (2012)Google Scholar
  9. 9.
    Indrusiak, L., dos Santos, O.: Fast and accurate transaction-level model of a wormhole network-on-chip with priority preemptive virtual channel arbitration. In: Design, Automation Test in Europe Conference (DATE), pp. 1–6 (2011)Google Scholar
  10. 10.
    Nayebi, A., Meraji, S., Shamaei, A., Sarbazi-Azad, H.: XMulator: a listener-based integrated simulation platform for interconnection networks. In: International Modeling Simulation (AMS), pp. 128–132 (2007)Google Scholar
  11. 11.
    Jiang, N., Becker, D., Michelogiannakis, G., Balfour, J., Towles, B., Shaw, D., Kim, J., Dally, W.: A detailed and flexible cycle-accurate network-on-chip simulator. In: IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 86–96 (2013)Google Scholar
  12. 12.
    Hosseinabady, M., Nunez-Yanez, J.: SystemC architectural transaction level modelling for large NoCs. In: Forum on Specification Design Languages (FDL), pp. 1–6 (2010)Google Scholar
  13. 13.
    Viaud, E., Potop-Butucaru, D., Greiner, A.: An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principles. In: Design, Automation and Test in Europe (DATE), pp. 1–6 (2006)Google Scholar
  14. 14.
    Suboh, S., Bakhouya, M., Gaber, J., El-Ghazawi, T.: Analytical modeling and evaluation of network-on-chip architectures. In: High Performance Computing and Simulation (HPCS), pp. 615–622 (2010)Google Scholar
  15. 15.
    Ogras, U., Bogdan, P., Marculescu, R.: An analytical approach for network-on-chip performance analysis. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 29(12), 2001–2013 (2010)CrossRefGoogle Scholar
  16. 16.
    van Moll, H., Corporaal, H., Reyes, V., Boonen, M.: Fast and accurate protocol specific bus modeling using TLM 2.0. In: Design, Automation Test in Europe (DATE), pp. 316–319 (2009)Google Scholar
  17. 17.
    Ghenassia, F.: Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems. Springer, New York (2006). Scholar
  18. 18.
    Gerstlauer, A., Dömer, R., Peng, J., Gajski, D.D.: System Design: A Practical Guide with SpecC. Springer, Heidelberg (2001). Scholar
  19. 19.
    Fulgham, M.L., Snyder, L.: Performance of chaos and oblivious routers under non-uniform traffic. Technical report (1993)Google Scholar
  20. 20.
    Mello, A., Tedesco, L., Calazans, N., Moraes, F.: Virtual channels in networks on chip: implementation and evaluation on hermes NoC. In: Integrated Circuits and System Design, pp. 178–183. ACM (2005)Google Scholar

Copyright information

© IFIP International Federation for Information Processing 2017

Authors and Affiliations

  • Ran Hao
    • 1
  • Nasibeh Teimouri
    • 1
  • Kasra Moazzemi
    • 1
  • Gunar Schirner
    • 1
  1. 1.Department of Electrical and Computer EngineeringNortheastern UniversityBostonUSA

Personalised recommendations