Circuit Vulnerabilities to Hardware Trojan at the Layout Level
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While the horizontal integrated circuit design process is extensively practiced, untrusted foundries can impose significant threats on the security of final products. A carefully-inserted extra circuitry as a Hardware Trojan in a circuit layout can interfere with circuit functionality under very rare circumstances with inconsiderable footprints. The fact necessitates comprehensive layout-level vulnerability analyses to evaluate the susceptibility of a circuit layout’s regions to hardware Trojan insertion. Further, there is a serious demand to metrics based on a circuit layout to quantify the possibility of hardware Trojan insertion in a specific region of layout.
- 1.ITC99 benchmarks. http://www.cad.polito.it/downloads/tools/itc99.html. Accessed 22 Jan 2018
- 2.Synopsys 90nm generic library for teaching ic design. http://www.synopsys.com/Community/UniversityProgram/Pages. Accessed 22 Jan 2018
- 3.L. Wang, C. Wu, X. Wen, VLSI Test Principles and Architectures: Design for Testability. The Morgan Kaufmann Series in Systems on Silicon (Morgan Kaufmann Publishers, San Francisco, 2006)Google Scholar
- 4.Ethernet 10GE MAC. http://opencores.org/project,xge_mac. Accessed 22 Jan 2018
- 5.Trust-HUB. https://www.trust-hub.org/. Accessed 22 Jan 2018