Fast DSE for Automated Parallelization of Embedded Legacy Applications

  • Kris HeidEmail author
  • Jakob WenzelEmail author
  • Christian HochbergerEmail author
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10824)


Mapping complex embedded applications to FPGA based SoCs often results in systems consisting of multiple processors to maintain high processing rates. Such systems can be created individually for each application, since FPGAs have very small non-recurring expenses. Thus, the system architecture (including the number of cores and the partitioning and distribution of tasks) must be derived and executed by the developer multiple times. In most cases it is not possible to analytically compute the design performance, so design space exploration comes into play. In this contribution we present a technique leveraging a combination of tools to (1) greatly reduce the effort to create different solutions in the design space and (2) reduce the time required for this design implementation by a factor of three. Compared to similar approaches, we claim to have a highly accurate design point evaluation and loosen the restrictions of the legacy application.


Field Programmable Gate Array (FPGA) Design Space Exploration RapidSoC Maximum Achievable Frequency Parallelization Tools 
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  1. 1.
    Abdallah, A.B.: Multicore Systems On-Chip: Practical Software/Hardware Design. Atlantis Press, Amsterdam (2013). Scholar
  2. 2.
    Cummiskey, P., Jayant, N., Flanagan, J.: Adaptive quantization in differential PCM coding of speech. Bell Syst. Techn. J. 52, 1105–1118 (1973)CrossRefGoogle Scholar
  3. 3.
    Dave, C., Bae, H., Min, S.J., Lee, S., Eigenmann, R., Midkiff, S.: Cetus: a source-to-source compiler infrastructure for multicores. Computer 42, 36–42 (2009)CrossRefGoogle Scholar
  4. 4.
    Ha, S., Lee, C., Yi, Y., Kwon, S., Joo, Y.P.: Hardware-software codesign of multimedia embedded systems: the peace approach. In: RTCSA (2006)Google Scholar
  5. 5.
    Heid, K., Wirsch, R., Hochberger, C.: Automated inference of SoC configuration through firmware source code analysis. In: FPGAs for Software Programmers (FSP), pp. 1–9 (2016)Google Scholar
  6. 6.
    Heid, K., Weber, J., Hochberger, C.: \(\upmu \)Streams: a tool for automated streaming pipeline generation on soft-core processors. In: FPGAs for General Purpose Computing (2016)Google Scholar
  7. 7.
    Hempel, G., Hochberger, C.: A resource optimized SoC kit for FPGAs. In: International Conference on Field Programmable Logic and Applications, pp. 761–764 (2007)Google Scholar
  8. 8.
    Kangas, T., Kukkala, P., Orsila, H., Salminen, E., Hännikäinen, M., Hämäläinen, T., Riihimäki, J., Kuusilinna, K.: UML-based MPSoC design framework. ACM TECS 5, 281–320 (2006)CrossRefGoogle Scholar
  9. 9.
    Keinert, J., Streubhr, M., Schlichter, T., Falk, J., Gladigau, J., Haubelt, C., Teich, J., Meredith, M.: SystemCoDesigner - an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications. ACM TODAES 14, 1:1–1:23 (2009)CrossRefGoogle Scholar
  10. 10.
    Kinsy, M.A., Pellauer, M., Devadas, S.: Heracles: a tool for fast RTL-based design space exploration of multicore processors. In: ACM/SIGDA FPGA, pp. 125–134 (2013)Google Scholar
  11. 11.
    Lavin, C., Padilla, M., Lamprecht, J., Lundrigan, P., Nelson, B., Hutchings, B.: HMFlow: accelerating FPGA compilation with hard macros for rapid prototyping. In: Field-Programmable Custom Computing Machines (FCCM), pp. 117–124 (2011)Google Scholar
  12. 12.
    Lavin, C., Padilla, M., Lundrigan, P., Nelson, B., Hutchings, B.: Rapid prototyping tools for FPGA designs: RapidSmith. In: FPT, pp. 353–356 (2010)Google Scholar
  13. 13.
    Monchiero, M., Canal, R., González, A.: Design space exploration for multicore architectures: a power/performance/thermal view. In: ICS, pp. 177–186 (2006)Google Scholar
  14. 14.
    Munk, H., Ayguadé, E., Bastoul, C., Carpenter, P., Chamski, Z., Cohen, A., Cornero, M., Dumont, P., Duranton, M., Fellahi, M., Ferrer, R., Ladelsky, R., Lindwer, M., Martorell, X., Miranda, C., Nuzman, D., Ornstein, A., Pop, A., Pop, S., Pouchet, L.N., Ramírez, A., Ródenas, D., Rohou, E., Rosen, I., Shvadron, U., Trifunović, K., Zaks, A.: ACOTES project: advanced compiler technologies for embedded streaming. Int. J. Parallel Program. 39, 397–450 (2010)CrossRefGoogle Scholar
  15. 15.
    Pop, A., Cohen, A.: OpenStream: expressiveness and data-flow compilation of OpenMP streaming programs. ACM TACO 9, 53 (2013)Google Scholar
  16. 16.
    Dolbeau, R., Bihan, S., Bodin, F.: HMPP: a hybrid multi-core parallel programming environment. In: Workshop on General Purpose Processing on GPU (2007)Google Scholar
  17. 17.
    Thompson, M., Nikolov, H., Stefanov, T., Pimentel, A.D., Erbas, C., Polstra, S., Deprettere, E.F.: A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs. In: IEEE/ACM/IFIP CODES+ISSS, pp. 9–14 (2007)Google Scholar
  18. 18.
    Wenzel, J., Hochberger, C.: RapidSoC: short turnaround creation of FPGA based SoCs. In: International Symposium on Rapid System Prototyping, pp. 86–92 (2016)Google Scholar

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© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Computer Systems GroupTechnische Universität DarmstadtDarmstadtGermany

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