Crossbar-Based Interconnection Networks pp 41-56 | Cite as

# Blocking Problem

## Abstract

This chapter focuses on the blocking problem. Different existing solutions to cope with this problem as well as their scalability will be analyzed. According to previous works, two main solutions are as follows: (1) Using small-size crossbar networks to build scalable interconnection networks with different topology compared to crossbar. Using this approach, many topologies have been introduced. Most of which are known as multistage interconnection networks. (2) Using small-size crossbar networks to build scalable crossbar networks. From this perspective, like to crossbar network, designed networks are non-blocking.

## 3.1 Introduction

In the early 50s, Neumann suggested a simple cost-effective design for electronic computers in which a single processing unit was connected to a single memory module. During the 60s, using the concept of solid-state components, the cost of large computing machines fell. Once it, very large-scale integration (VLSI) is evolved in which thousands of transistors placed on a single chip. Supercomputers were successfully deal with scientific issues such as climate modeling, aerodynamic aircraft design, and particle physics, which created a strong incentive for the development of parallel computers. After the 80s, this technology has played an undeniable role in solving other challenging issues [1].

As discussed in Chap. 1, processors, memory hierarchy, and the interconnection network are vital parts of a parallel system. In other words, the design of an efficient interconnection network is crucial for the efficient construction of multiprocessor systems [2, 3, 4, 5].

One of the important factors for choosing a proper interconnection topology is to take into account the blocking problem. If a network is able to handle all possible requests each of which are as a permutation (i.e., defined as a request for parallel connections of each \( N \) sources to \( N \) corresponding distinct destinations), then the network is non-blocking. As a result, a network is blocking, if it is unable to handle all such requests without conflict and blocking [2, 6, 7, 8].

So far, a large number of interconnection topologies have been introduced. However, a few of them can efficiently resolve the blocking problem. For systems with \( N \) terminal nodes, a topology would be ideal, if that can connect these nodes by a single switch of size \( N \times N \). This type of topology is known as crossbar. In a crossbar network, any processor in the system can connect to any other processor or memory module so that many processors can communicate simultaneously without contention. Clearly, a crossbar network is strictly non-blocking to any permutation of connections. Here, a question arises is that if the crossbar network is strictly non-blocking, whether blocking problem can be considered as a solved problem? Unfortunately, the answer is no. There is an important problem in the use of crossbar network, namely scalability. The number of available pins and the area of the wiring make limit in the size of the largest crossbar implemented by a single chip. Although the technology of VLSI can integrate the crossbar switch hardware into a single chip, the number of pins within a single VLSI chip cannot exceed a certain number [2, 6, 9]. The scalability problem will prevent the direct use of crossbar network for large-size systems. Therefore, crossbar network can be used in small-size multiprocessor systems in practice. To tackle this issue, there is a reasonable solution to take advantage of crossbar networks in systems with large sizes. This solution offers the use of small-size crossbars as building blocks for networks with larger sizes. By studying the pervious works, it can be deduced that this solution can be implemented by two different approaches:

(1) Designing different scalable interconnection networks topology compared to crossbar, using small-size crossbar networks as switching elements [2, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]. So far, a large number of interconnection topologies are designed using this approach that most of them are known as multistage interconnection networks. (2) Designing scalable crossbar networks using small-size crossbar networks as switching elements [2, 6, 33]. This approach can lead to the design of scalable networks, which are non-blocking similar to crossbar network.

In the remainder of this chapter, the two aforementioned approaches will be discussed more detailed. Next, in Chap. 4 on behalf of the first approach, several approaches will be introduced to improve fault-tolerance metric (as a way to improve blocking problem) in multistage interconnection networks. Then, in Chap. 5, a new non-blocking interconnection topology will be proposed on behalf of the second approach.

## 3.2 Related Works

As discussed in the previous section, crossbar network suffers from scalability problem to exploit in large-size systems. The main reason for this problem is that a large number of pins are required to implement a large-size crossbar network on a single VLSI chip. However, the number of pins in a VLSI chip cannot exceed a few hundred. This will result in restrictions on the size of crossbar network. The solution to deal with this problem is the use of small-size crossbars as building blocks of larger networks. On the other hand, two different scenarios can implement this solution: (1) Take advantage of small-size crossbar networks as switching elements to build larger networks that differ with crossbar, topologically [2, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]. (2) Take advantage of small-size crossbar networks as switching elements to build larger crossbar networks that are equivalent to the crossbar, topologically [2, 6, 33]. We will discuss these two different scenarios in sub-Sects. 3.2.1 and 3.2.2, respectively.

### 3.2.1 Construction of Scalable Non-crossbar Networks by Small-Size Crossbars

This approach can be used as a base for making different topologies. In what follows, important interconnection topologies made based on this approach have been investigated:

Generally, when it is discussed about the banyan-type network in the literature, the purpose of it is a typical multistage interconnection network (MIN) that can provide only a single path between each pair of source–destination. Therefore, the network faces with single-point-of-failure and fails in the event of a failure in one of its components. So far, a variety of banyan-type topologies such as shuffle-exchange network, omega network, baseline network, binary n-cube network, and delta networks are presented by researchers. The remarkable thing is that all of these types of networks typically have used 2 × 2 crossbar networks as their switching elements.

As can be seen, all topologies discussed in this subsection use the small-size crossbar networks as their constituent elements. Since each of these small-size crossbar switches can be implemented in a single chip, scalability problem can be easily solved. However, these topologies that are mostly of the type of multistage interconnection networks are incapable of providing an efficient solution to the blocking problem. Below, we will examine the reasons of this issue:

In a general view, MINs can be divided into two main groups: (1) single-path MINs (banyan-type) and (2) multipath MINs. Single-path MINs are the ones that cannot provide more than one path between each pair of source–destination. This structure can lead to the blocking problem, since the request for a new connection may be impossible due to busy resources such as links and switches by other existing connections. That is why these networks are known as blocking MINs. In contrast to these single-path networks, there are multipath MINs that can provide more than one path between each pair of source–destination. When a path is not available, then the network can switch to alternative path to handle a connection request. As a result, the existence of multiple paths in the network can improve fault-tolerance capability and reduce the occurrence of the blocking problem. According to this argument, one of the approaches to alleviate the blocking problem is improving fault-tolerance feature on the network. For this reason, fault tolerance in MINs is one of the favorite topics among researchers. Therefore, because of the importance of fault-tolerance parameter in multistage interconnection networks, the next chapter is devoted to a discussion on some new approaches to improve this feature in these networks.

Fault-tolerant MINs are of interest because of cost-effectiveness compared to crossbar network. However, most of these networks cannot provide a fully non-blocking mode that needs to manage all conflicts. Thus, most of this kind of MINs are also considered as blocking MINs. Only two classes of fault-tolerant MINs that may be able to solve the blocking problem are as follows: (1) rearrangeable non-blocking (or simply rearrangeable) MINs such as Benes network [31] and (2*n* − 1)-Stage Shuffle-Exchange Networks \( (n = \log_{2} N) \) [28, 29, 30] and (2) non-blocking Clos network [32].

The main idea of the rearrangeable network to deal with the blocking problem is re-arrangement of connections. This network can respond to all connections requests in every permutation by re-arrangement of current connections if needed. At first glance, these networks seem to be efficient solution in theory. Nevertheless, there are some problems in practice with a closer look: (a) In uninterruptible applications, re-arrangement of existing connections is not acceptable [33]. (b) Rearrangeable networks need a central controller to re-arrangement of connections. However, it is very difficult to re-arrangement of connections, since the access of the processor to the network is asynchronously. In fact, when accesses are asynchronous, rearrangeable networks act like blocking networks [2].

If a network can successfully handle all possible permutations without re-arrangement of current connections, then the network is non-blocking. Clos network is the most well-known non-blocking MIN. In essence, the Clos network is a three-stage MIN that each stage is made of some crossbar switches. However, other Clos network with an odd number of switching stages can be built recursively by pasting a three-stage Clos network instead of the switches located in middle stage. A symmetric Clos can be defined by triple of \( \left( {m,n,r} \right) \), where \( m \) is the number of switches located in the middle stage, \( n \) is the number of incoming links for each switch in the first stage and the number of outgoing links for each switch in the last stage, and \( r \) is the number of switches in each of the first and last stages. In addition, size of crossbar switches located on the first stage, the middle stage, and the last stage is \( n \times m \), \( r \times r \), and \( m \times n \), respectively. Although the Clos network can be non-blocking in theory, there are some important issues in the way of this solution in practice: (a) It has been proven that Clos is non-blocking if this condition be true: \( m \ge 2n - 1 \) [6, 16]. Therefore, there are some structural constraints for a non-blocking Clos. (b) An efficient control mechanism for the allocation of connections in the Clos is essential. However, this mechanism is usually complex in a Clos network [6, 19, 33, 34, 35, 36]. For routing a packet in the Clos, after it was sent to switch on the first stage, each switch in the middle stage can be considered for forwarding packet, as long as the link connected to the switch is free. Also, this middle switch should choose a free link to switch on the last stage. Here, when this link is busy, the path is impossible. Finally, switch on the last stage should choose the selected outgoing link. Thus, the problem of routing in the Clos is largely dependent on an efficient mechanism for the allocation of each packet to a middle-stage switch.

Altogether, according to the discussions in this section, it can be said that MINs can solve the scalability problem raised in the crossbar network. On the other hand, although these networks cannot fully cope with the blocking problem, they can support the important metric of fault tolerance that can result in reducing the blocking problem. Therefore, fault-tolerant MINs are of particular importance in this area. In Chap. 4, some important methods to improve the fault-tolerance metric on MINs will be examined.

### 3.2.2 Construction of Scalable Crossbar Topologies by Small-Size Crossbars

In this approach, the idea is to build large-size crossbar networks using the small-size networks as switching elements. This approach can have several important advantages: First, the blocking problem can easily be solved, because the crossbar networks are strictly non-blocking. Second, the issue of scalability can be solved by the use of small-size crossbars. Therefore, this approach can be a more efficient solution compared to that approach discussed in the previous subsection. In this area, some ideas can be found in [2, 6]. However, the number of topologies designed based on this approach is very low. A rare instance of this type of topology is Multistage Crossbar Network (MCN) [33]. MCN is a multistage implementation of crossbar architecture and it uses small-size crossbar networks as switching elements.

MCN can be a reasonable solution to the problem of scalability. However, disadvantage of this structure is its high hardware cost. The hardware cost of a network can be calculated based on the total number of crosspoints in it [7, 10, 22, 27, 35]. According to this definition, the hardware cost of the crossbar network is equal to \( N^{2} \). In addition, the number of 2 × 2 crossbar switches in the MCN is equal to \( N^{2} \); thus, its cost is \( 4N^{2} \). The cost of the MCN is not acceptable, because it is four times higher than the cost of typical crossbar network.

In view of the discussions that took place in this subsection, design of scalable crossbar networks using small-size crossbar switches is a good idea for construction of scalable non-blocking interconnection networks. However, in a few interconnection topologies, this approach has been used in their design. MCN is a network built based on this approach and it can solve the problems of blocking and scalability. However, it has four times higher hardware cost compared to typical crossbar network. Therefore, other designs should be provided to achieve better performance compared to MCN in terms of cost. For this purpose, a new interconnection topology named Scalable Crossbar Network (SCN) will be discussed in Chap. 5. SCN is designed based on the approach discussed in this subsection and it brings the following advantages: (1) It is a non-blocking network. (2) It can solve the problem of scalability using small-size crossbar networks as switching elements in its structure. (3) It has a same hardware cost compared to typical crossbar network.

As will be discussed in Chap. 5, SCN can meet all the above requirements. In addition, the routing mechanism for the SCN network can be fast, cost-effectiveness, and self-routing. In addition, performance analysis conducted in Chap. 5 demonstrates that the SCN can obtain very good performance in terms of various important metrics including terminal reliability, mean time to failure, and system failure rate compared to different interconnection topologies namely SEN, SEN+, Benes network, replicated MIN, multilayer MINs, and MCN.

## References

- 1.Jadhav SS (2009)
*Advanced computer architecture and computing*. Technical PublicationsGoogle Scholar - 2.Duato J, Yalamanchili S, Ni LM (2003) Interconnection networks: an engineering approach. Morgan Kaufmann, USAGoogle Scholar
- 3.Dubois M, Annavaram M, Stenström P (2012)
*Parallel computer organization and design*. Cambridge University Press, CambridgeCrossRefGoogle Scholar - 4.Culler DE, Singh JP, Gupta A (199)
*Parallel computer architecture: a hardware/software approach*. Morgan KaufmannGoogle Scholar - 5.Agrawal DP (1983) Graph theoretical analysis and design of multistage interconnection networks. IEEE Trans Comput 100(7):637–648CrossRefGoogle Scholar
- 6.Dally WJ, Towels BP (2004) Principles and practices of interconnection networks. Morgan Kaufmann, San Francisco, Calif, USAGoogle Scholar
- 7.Bistouni F, Jahanshahi M (2014) Improved extra group network: a new fault-tolerant multistage interconnection network. J Supercomput 69(1):161–199CrossRefGoogle Scholar
- 8.Villar JA et al (2013) An integrated solution for QoS provision and congestion management in high-performance interconnection networks using deterministic source-based routing. J Supercomput 66(1):284–304CrossRefGoogle Scholar
- 9.Hur JY et al (2007) Systematic customization of on-chip crossbar interconnects.
*Reconfigurable computing: architectures, tools and applications*. Springer Berlin Heidelberg, pp 61–72Google Scholar - 10.Bistouni F, Jahanshahi M (2015) Pars network: a multistage interconnection network with fault-tolerance capability. J Parallel Distrib Comput 75:168–183CrossRefGoogle Scholar
- 11.Bistouni F, Jahanshahi M (2014) Analyzing the reliability of shuffle-exchange networks using reliability block diagrams. Reliab Eng Syst Saf 132:97–106CrossRefGoogle Scholar
- 12.Parker DS, Raghavendra CS (1984) The gamma network. IEEE Trans Comput 100(4):367–373CrossRefGoogle Scholar
- 13.Rajkumar S, Goyal NK (2014) Design of 4-disjoint gamma interconnection network layouts and reliability analysis of gamma interconnection networks. J Supercomput 69(1):468–491CrossRefGoogle Scholar
- 14.Chen CW, Chung CP (2005) Designing a disjoint paths interconnection network with fault tolerance and collision solving. J Supercomput 34(1):63–80MathSciNetCrossRefGoogle Scholar
- 15.Nitin SG, Srivastava N (2011) Designing a fault-tolerant fully-chained combining switches multi-stage interconnection network with disjoint paths. J Supercomput 55(3):400–431CrossRefGoogle Scholar
- 16.Wei S, Lee G (1988) Extra group network: a cost-effective fault-tolerant multistage interconnection network. ACM SIGARCH Comput Archit News 16(2) IEEE Computer Society PressCrossRefGoogle Scholar
- 17.Matos D et al (2013) Hierarchical and multiple switching NoC with floorplan based adaptability. Reconfigurable computing: architectures, tools and applications. Springer, Berlin, Heidelberg, pp 179–184Google Scholar
- 18.Kumar VP, Reddy SM (1987) Augmented shuffle-exchange multistage interconnection networks. Computer 20(6):30–40CrossRefGoogle Scholar
- 19.Vasiliadis DC, Rizos GE, Vassilakis C (2013) Modelling and performance study of finite-buffered blocking multistage interconnection networks supporting natively 2-class priority routing traffic. J Netw Comput Appl 36(2):723–737CrossRefGoogle Scholar
- 20.Gunawan I (2008) Reliability analysis of shuffle-exchange network systems. Reliab Eng Syst Saf 93(2):271–276CrossRefGoogle Scholar
- 21.Blake JT, Trivedi KS (1989) Reliability analysis of interconnection networks using hierarchical composition. IEEE Trans Reliab 38(1):111–120CrossRefGoogle Scholar
- 22.Bansal PK, Joshi RC, Singh K (1994) On a fault-tolerant multistage interconnection network. Comput Electr Eng 20(4):335–345CrossRefGoogle Scholar
- 23.Blake JT, Trivedi KS (1989) Multistage interconnection network reliability. IEEE Trans Comput 38(11):1600–1604CrossRefGoogle Scholar
- 24.Nitin, Subramanian A (2008) Efficient algorithms and methods to solve dynamic MINs stability problem using stable matching with complete ties. J Discrete Algorithms 6(3):353–380MathSciNetCrossRefGoogle Scholar
- 25.Fan CC, Bruck J (2000) Tolerating multiple faults in multistage interconnection networks with minimal extra stages. IEEE Trans Comput 49(9):998–1004CrossRefGoogle Scholar
- 26.Adams GB, Siegel HJ (1982) The extra stage cube: a fault-tolerant interconnection network for supersystems. IEEE Transac Comput 100(5):443–454CrossRefGoogle Scholar
- 27.Tutsch D, Hommel G (2008) MLMIN: a multicore processor and parallel computer network topology for multicast. Comput Oper Res 35(12):3807–3821CrossRefGoogle Scholar
- 28.Çam H (2001) Analysis of shuffle-exchange networks under permutation trafic. Switching networks: recent advances. Springer, USA, pp 215–256Google Scholar
- 29.Çam H (2003) Rearrangeability of (2n − 1)-stage shuffle-exchange networks. SIAM J Comput 32(3):557–585MathSciNetCrossRefGoogle Scholar
- 30.Dai H, Shen X (2008) Rearrangeability of 7-stage 16 × 16 shuffle exchange networks. Front Electr Electron Eng China 3(4):440–458CrossRefGoogle Scholar
- 31.Beneš VE (1965) Mathematical theory of connecting networks and telephone traffic, vol 17. Academic PressGoogle Scholar
- 32.Clos C (1953) A study of non-blocking switching networks. Bell Syst Tech J 32(2):406–424CrossRefGoogle Scholar
- 33.Kolias C, Tomkos I (2005) Switch fabrics. IEEE Circ Devices Mag 21(5):12–17CrossRefGoogle Scholar
- 34.Fey D et al (2012) Optical multiplexing techniques for photonic Clos networks in high performance computing architectures. J Supercomput 62(2):620–632CrossRefGoogle Scholar
- 35.Cuda D, Giaccone P, Montalto M (2012) Design and control of next generation distribution frames. Comput Netw 56(13):3110–3122CrossRefGoogle Scholar
- 36.Sibai FN (2011) Design and evaluation of low latency interconnection networks for real-time many-core embedded systems. Comput Electr Eng 37(6):958–972CrossRefGoogle Scholar